IP Library Granted Patent US 10,651,266
Granted Patent B2
US 10,651,266 · App. 16/052,161 · Granted May 12, 2020

Efficient metal-insulator-metal capacitor

Inventors: Kisup Chung (Albany, NY); Isabel C. Estrada-Raygoza (Albany, NY); Hemanth Jagannathan (Niskayuna, NY); Chi-Chun Liu (Altamont, NY); Yann A. M. Mignot (Slingerlands, NY); Hao Tang (Albany, NY)
Assignee: Tessera, Inc.
H01L28/60
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Quick Facts
Patent No.
US 10,651,266
App. No.
16/052,161
Granted
May 12, 2020
Kind
B2
Abstract

Capacitors include a stack that has a first metallic layer formed over a substrate with at least one high domain and at least one low domain, an insulator formed over the first metallic layer, and a second metallic layer formed over the insulator. A bottom contact is formed in the substrate having a top surface that is even with a top surface of the substrate in the at least one high domain. A cap layer is formed directly on the substrate in the high domains, under the stack.

Claims (42)

1. A capacitor, comprising:

a stack, comprising:

a first metallic layer formed over a substrate that comprises at least one high domain and at least one low domain, where a surface of the substrate in the at least one low domain has a height that is lower than a surface of the substrate in the at least one high domain;

an insulator formed over the first metallic layer; and

a second metallic layer formed over the insulator;

a bottom contact formed in the substrate having a top surface that is even with a top surface of the substrate in the at least one high domain; and

a cap layer formed directly on the substrate in the high domains, under the stack.

2. The capacitor of claim 1 , wherein the cap layer is absent over the low domains.

3. The capacitor of claim 1 , further comprising:

a protective layer formed over the stack; and

a dielectric layer formed over and around the protective layer and the stack.

4. The capacitor of claim 3 , further comprising a top contact that penetrates the dielectric layer and the protective layer to form an electrical contact with the top metallic layer.

5. The capacitor of claim 1 , wherein the first metallic layer has low domain with a bottom surface that is lower than a bottom surface of the bottom contact.

6. The capacitor of claim 1 , wherein the second metallic layer comprises a single-walled downward extension above a low domain.

7. The capacitor of claim 1 , wherein the first metallic region comprises a plurality of low regions, including a low region over the bottom contact and at least one additional low region.

8. A capacitor, comprising:

a stack, comprising:

a first metallic layer formed over a substrate that comprises at least one high domain and a plurality of low domains, where a surface of the substrate in the at least one low domain has a height that is lower than a surface of the substrate in the at least one high domain;

an insulator formed over the first metallic layer; and

a second metallic layer formed over the insulator;

a bottom contact formed in the substrate under a first low domain of the first metallic layer, having a top surface that is even with a top surface of the substrate in the at least one high domain; and

a cap layer formed directly on the substrate in the high domains, under the stack.

9. The capacitor of claim 8 , wherein the cap layer is absent over the low domains.

10. The capacitor of claim 8 , further comprising:

a protective layer formed over the stack; and

a dielectric layer formed over and around the protective layer and the stack.

11. The capacitor of claim 10 , further comprising a top contact that penetrates the dielectric layer and the protective layer to form an electrical contact with the top metallic layer.

12. The capacitor of claim 8 , wherein the first metallic layer has low domain with a bottom surface that is lower than a bottom surface of the bottom contact.

13. The capacitor of claim 8 , wherein the second metallic layer comprises a single-walled downward extension above a low domain.

14. A capacitor, comprising:

a stack, comprising:

a first metallic layer formed over a substrate that comprises at least one high domain and at least one low domain, where a surface of the substrate in the at least one low domain has a height that is lower than a surface of the substrate in the at least one high domain;

an insulator formed over the first metallic layer; and

a second metallic layer formed over the insulator;

a bottom contact formed in the substrate in electrical contact with the first metallic layer, having a top surface that is even with a top surface of the substrate in the at least one high domain;

a cap layer formed directly on the substrate in the high domains, under the stack;

a protective layer formed over the stack;

a dielectric layer formed over and around the protective layer and the stack; and

a top contact that penetrates the dielectric layer and the protective layer to form an electrical contact with the top metallic layer.

15. The capacitor of claim 14 , wherein the cap layer is absent over the low domains.

16. The capacitor of claim 14 , wherein the first metallic layer has low domain with a bottom surface that is lower than a bottom surface of the bottom contact.

17. The capacitor of claim 14 , wherein the second metallic layer comprises a single-walled downward extension above a low domain.

Assignments (6)
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 073658/0771 →
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 073658/0868 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 16/161,111 PREVIOUSLY RECORDED ON REEL 051489 FRAME 0324. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Aug 3, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: TESSERA, INC.
Reel/Frame 053389/0252 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: TESSERA, INC.
Reel/Frame 051489/0324 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2018
From: CHUNG, KISUP; ESTRADA-RAYGOZA, ISABEL C.; JAGANNATHAN, HEMANTH; LIU, CHI-CHUN; MIGNOT, YANN A.M.; TANG, HAO
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 046527/0768 →