Fabrication of a vertical fin field effect transistor with reduced dimensional variations
View Patent ↗A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of vertical fins within the perimeter of the fin pattern region, including border fins at the perimeter of the fin pattern region and interior fins located within the perimeter and inside the bounds of the border fins, wherein the border fins are formed from the dummy fin fill, and removing the border fins, wherein the border fins are dummy fins and the interior fins are active vertical fins.
1. A method of forming arrays of fin field effect transistors (finFETs) having fin(s) with reduced dimensional variations, comprising:
forming a first array of vertical fins, a second array of vertical fins, and one or more dummy fins on a substrate, wherein the one or more dummy fins are on a dummy fin fill between the first array of vertical fins and the second array of vertical fins; and
removing the one or more dummy fins and dummy fin fill to form a step in the substrate and a gap between the first array of vertical fins and the second array of vertical fins.
2. The method of claim 1 , wherein the one or more dummy fins are made of amorphous silicon (a-Si), poly-crystalline silicon (p-Si), amorphous silicon-germanium (a-SiGe), or poly-crystalline silicon-germanium (p-SiGe).
3. The method of claim 2 , wherein the vertical fins are single crystal silicon, and the one or more dummy fins are removed by a selective HCl etch.
4. The method of claim 3 , further comprising forming a bottom spacer between each pair of the vertical fins and an isolation region in the gap.
5. The method of claim 4 , wherein the bottom spacers are silicon oxide (SiO), a high-k metal oxide, silicon nitride (SiN), or silicon oxynitride (SiON).
6. The method of claim 1 , wherein the first array of vertical fins is an N column by M row arrangement of vertical fins, and the second array of vertical fins is an X column by Y row arrangement of vertical fins, where X is different than N and Y is different from M.
7. The method of claim 6 , wherein the one or more dummy fins are located the same pitch distance from an adjacent vertical fin, as the pitch between adjacent vertical fins in the first array.
8. The method of claim 7 , further comprising forming a first doped region in the substrate below the first array of vertical fins, and a second doped region in the substrate below the second array of vertical fins.
9. The method of claim 8 , further comprising forming a punch-through stop in a lower portion of the vertical fins in the first array.
10. The method of claim 9 , further comprising forming a top source/drain on the vertical fins in the first array.
11. A method of forming arrays of fin field effect transistors (finFETs) having fin(s) with reduced dimensional variations, comprising:
forming a first array of vertical fins, wherein the first array of vertical fins is an N column by M row pattern;
forming a second array of vertical fins, wherein the second array of vertical fins is an X column by Y row pattern;
forming an array of at least one column of M dummy fins on a dummy fin fill between the first array of vertical fins and the second array of vertical fins; and
removing the array of M dummy fins and dummy fin fill to form a step in the substrate and a gap between the neighboring arrays of vertical fins.
12. The method of claim 11 , wherein the one or more dummy fins are made of amorphous silicon (a-Si), poly-crystalline silicon (p-Si), amorphous silicon-germanium (a-SiGe), or poly-crystalline silicon-germanium (p-SiGe).
13. The method of claim 12 , wherein the vertical fins are single crystal silicon, and the one or more dummy fins are removed by a selective HCl etch.
14. The method of claim 13 , further comprising forming a bottom spacer between each pair of the vertical fins and an isolation region in the gap.
15. The method of claim 14 , wherein the bottom spacers are silicon oxide (SiO), a high-k metal oxide, silicon nitride (SiN), or silicon oxynitride (SiON).
16. A method of forming arrays of fin field effect transistors (finFETs) having fin(s) with reduced dimensional variations, comprising:
forming a first array of vertical fins, wherein the first array of vertical fins is an N column by M row pattern;
forming a second array of vertical fins, wherein the second array of vertical fins is an X column by Y row pattern;
forming a first array of at least one column of M dummy fins on a dummy fin fill between the first array of vertical fins and the second array of vertical fins;
forming a first doped region in the substrate below the first array of vertical fins;
forming a second doped region in the substrate below the second array of vertical fins; and
removing the array of M dummy fins and dummy fin fill to form a step in the substrate and a gap between the neighboring arrays of vertical fins.
17. The method of claim 16 , further comprising forming a second array of at least one column of M dummy fins on the side of the first array of vertical fins opposite the first array of at least one column of M dummy fins.
18. The method of claim 17 , further comprising forming a third array of at least one column of Y dummy fins on the opposite side of the second array of vertical fins.
19. The method of claim 17 , further comprising forming a row of N dummy fins on each of opposite sides of the first array of vertical fins, such that dummy fins form a perimeter around the first array of vertical fins, wherein the first array of vertical fins form interior fins.
20. The method of claim 17 , further comprising forming a gate structure on the vertical fins in the first array, and forming a top source/drain on each of the vertical fins in the first array to form a multi-fin vertical field effect transistor.