Fabrication of a vertical fin field effect transistor with reduced dimensional variations
A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of vertical fins within the perimeter of the fin pattern region, including border fins at the perimeter of the fin pattern region and interior fins located within the perimeter and inside the bounds of the border fins, wherein the border fins are formed from the dummy fin fill, and removing the border fins, wherein the border fins are dummy fins and the interior fins are active vertical fins.
1. A method of forming one or more fins of a fin field effect transistor (finFET), the method comprising:
providing a substrate comprising a first material;
forming one or more trenches in the substrate;
filling the trenches with a trench-filling material comprising a second material that is different from the first material to form a trench-filled substrate;
forming one or more vertical fins comprising the first material and one or more dummy fins comprising the second material; and
subsequently etching the one or more dummy fins as part of a fin-cut process.
2. The method of claim 1 , wherein the one or more dummy fins and the one or more vertical fins are formed at the same time using a directional etch.
3. The method of claim 2 , wherein the first material and the second material have about the same etch rate for the directional etch used to form the one or more dummy fins and the one or more vertical fins.
4. The method of claim 1 , wherein the first material is silicon and the second material is silicon germanium.
5. The method of claim 1 , wherein at least one of the one or more vertical fins is directly adjacent to at least one of the one or more dummy fins.
6. The method of claim 1 , further comprising planarizing the trench-filled substrate to obtain a substantially flat surface prior to forming the one or more vertical fins and the one or more dummy fins.
7. The method of claim 6 , wherein forming the one or more vertical fins and forming the one or more dummy fins comprises:
forming multiple layers including a mandrel layer over the trench-filled substrate; and
patterning the mandrel layer to form a plurality of mandrels;
forming sidewall spacers on the plurality of mandrels;
removing the plurality of mandrels; and
etching the trench-filled substrate to transfer the pattern formed by the sidewall spacers into the trench-filled substrate.
8. The method of claim 6 , wherein planarizing the trench-filled substrate comprises using a chemical-mechanical polishing (CMP) process.
9. The method of claim 1 , further comprising:
depositing a dielectric layer over the one or more vertical fins after etching the one or more dummy fins as part of a fin-cut process; and
etching the dielectric layer to expose upper portions of the one or more vertical fins.
10. The method of claim 1 , wherein etching the one or more dummy fins as part of a fin-cut process comprises a selective etch.
11. A method of forming an integrated circuit comprising one or more fins, the method comprising:
providing a substrate comprising a first material;
forming one or more trenches in the substrate;
filling the trenches with a trench-filling material comprising a second material that is different from the first material to form a trench-filled substrate;
forming one or more vertical fins comprising the first material and one or more dummy fins comprising the second material; and
subsequently etching the one or more dummy fins as part of a fin-cut process, wherein the fin-cut process defines a border between adjacent fin pattern regions.
12. The method of claim 11 , wherein the adjacent fin pattern regions comprise different fin pitches.
13. The method of claim 11 , wherein the adjacent fin pattern regions comprise different fin sizes.
14. The method of claim 11 , wherein the adjacent fin pattern regions comprise different array dimensions.
15. The method of claim 11 , wherein etching the one or more dummy fins as part of a fin-cut process comprises a selective etch.
16. The method of claim 11 , wherein the one or more dummy fins and the one or more vertical fins are formed at the same time using a directional etch.
17. The method of claim 12 , wherein the first material and the second material have about the same etch rate for the etch used to form the one or more dummy fins and the one or more vertical fins.
18. The method of claim 11 , wherein the first material is silicon and the second material is silicon germanium.
19. The method of claim 11 , wherein at least one of the one or more vertical fins is directly adjacent to at least one of the one or more dummy fins.
20. The method of claim 11 , further comprising planarizing the trench-filled substrate to obtain a substantially flat surface prior to forming the one or more vertical fins and the one or more dummy fins.