IP Library Granted Patent US 10,770,347
Granted Patent B2
US 10,770,347 · App. 16/657,169 · Granted Sep 8, 2020

Interconnect structure

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Quick Facts
Patent No.
US 10,770,347
App. No.
16/657,169
Granted
Sep 8, 2020
Kind
B2
Abstract

Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.

Claims (35)

1. A method of making an interconnect structure comprising:

forming a copper interconnect structure in a dielectric material;

forming a capping layer in contact with a top surface of the copper interconnect structure, wherein an interface of a bottom surface of the capping layer and the top surface of the copper interconnect structure is co-planar with a top surface of the dielectric material; and

forming a barrier layer outdiffused from a top surface and side surfaces of the capping layer,

wherein the copper interconnect structure comprises:

a layer of Tantalum Nitride (TaN);

a layer of CuMn directly on the TaN layer; and

an electroplated copper layer on the CuMn layer.

2. The method of claim 1 , wherein the capping layer comprises Ru and the barrier layer comprises MnO.

3. The method of claim 2 , further comprising forming a barrier layer at an interface of the copper interconnect structure and the dielectric material.

4. The method of claim 1 , wherein the capping layer comprises cobalt and the barrier layer comprises MnO.

5. The method of claim 4 , further comprising forming a barrier layer at an interface of the copper interconnect structure and the dielectric material.

6. The method of claim 5 , further comprising oxidizing the capping layer.

7. The method of claim 1 , wherein the capping layer extends entirely across a topmost surface of the copper interconnect structure.

8. The method of claim 1 , wherein the barrier layer comprises Mn outdiffused from the CuMn layer to an upper surface of the capping layer during an anneal process.

9. A method of making an interconnect structure comprising:

forming an interconnect structure in a dielectric material;

forming a capping layer in contact with a top surface of the interconnect structure, wherein an interface of a bottom surface of the capping layer and the top surface of the interconnect structure is co-planar with a top surface of the dielectric material; and

forming a barrier layer outdiffused from a top surface and side surfaces of the capping layer,

wherein the interconnect structure comprises:

a layer of Tantalum Nitride (TaN);

a layer of CuMn on the TaN layer; and

an electroplated copper layer on the CuMn layer.

10. The method of claim 9 , wherein the capping layer comprises Ru and the barrier layer comprises MnO.

11. The method of claim 10 , further comprising forming a barrier layer at an interface of the interconnect structure and the dielectric material.

12. The method of claim 9 , wherein the capping layer comprises cobalt and the barrier layer comprises MnO.

13. The method of claim 12 , further comprising forming a barrier layer at an interface of the interconnect structure and the dielectric material.

14. The method of claim 13 , further comprising oxidizing the capping layer.

15. The method of claim 9 , wherein the capping layer extends entirely across a topmost surface of the interconnect structure.

16. The method of claim 9 , wherein the barrier layer comprises Mn outdiffused from the CuMn layer to an upper surface of the capping layer during an anneal process.

17. A method of making an interconnect in a semiconductor structure, the method comprising:

forming a self-aligned barrier layer on a capping layer by outdiffusing atoms from an underlying layer, through both a first layer and the capping layer, to an outer surface of the capping layer.

18. The method of claim 17 , wherein the underlying layer comprises Mn and the atoms are Mn atoms.

19. The method of claim 17 , wherein the self-aligned barrier layer is provided over at least a top surface of the capping layer.

20. The method of claim 17 , wherein the capping layer comprises Ru and the barrier layer comprises MnO.

Assignments (6)
CHANGE OF NAME Recorded Sep 27, 2024
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 069067/0410 →
CERTIFICATE OF CONVERSION & CHANGE OF NAME Recorded Sep 7, 2022
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 061388/0199 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 16/161,111 PREVIOUSLY RECORDED ON REEL 051489 FRAME 0324. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Aug 3, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: TESSERA, INC.
Reel/Frame 053389/0252 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: TESSERA, INC.
Reel/Frame 051489/0324 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2019
From: EDELSTEIN, DANIEL C.; NGUYEN, SON V.; NOGAMI, TAKESHI; PRIYADARSHINI, DEEPIKA; SHOBHA, HOSADURGA K.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 050761/0010 →