STABLE WORK FUNCTION FOR NARROW-PITCH DEVICES
A work function setting metal stack includes a configuration of layers including a high dielectric constant layer and a diffusion prevention layer formed on the high dielectric constant layer. An aluminum doped TiC layer has a thickness greater than 5 nm wherein the configuration of layers is employed between two regions as a diffusion barrier to prevent mass diffusion between the two regions.
1 . A method for forming a gate structure for a field effect transistor, comprising:
forming a gate dielectric layer over and between a plurality of fins;
depositing a single diffusion prevention layer on the gate dielectric; and
depositing a TiAlC layer on the diffusion prevention layer by pinching off portions of the TiAlC layer within the diffusion prevention layer to merge the portions without intervening layers between the portions.
2 . The method as recited in claim 1 , wherein the fins include semiconductor fins and the method includes forming an interface layer on the semiconductor fins.
3 . The method as recited in claim 1 , wherein the fins include two or more stacked nanosheets and the method includes patterning the nanosheets to form the fins, the nanosheets each including a semiconductor layer and the semiconductor layers are separated by a work function setting metal stack including a high dielectric constant layer; a diffusion prevention layer formed on the high dielectric constant layer; and an aluminum doped TiC layer having a thickness greater than 5 nm.
4 . The method as recited in claim 1 , wherein the diffusion prevention layer includes a TiN layer.
5 . The method as recited in claim 1 , wherein doping the TiC layer with aluminum includes providing an aluminum concentration of between about 20% and about 40%.
6 . The method as recited in claim 1 , wherein the gate dielectric layer includes a high dielectric constant layer.
7 . A method for forming a field effect transistor, comprising:
forming a gate dielectric layer over and between a plurality of fins;
depositing a single diffusion prevention layer on the gate dielectric;
depositing a TiAlC layer having a thickness greater than 5 nm on the diffusion prevention layer by pinching off portions of the TiAlC layer within the diffusion prevention layer to merge the portions without intervening layers between the portions; and
forming source and drain regions on sides of the gate structure on the plurality of fin structures.
8 . The method as recited in claim 7 , wherein the fins include semiconductor fins and the method includes forming an interface layer on the semiconductor fins.
9 . The method as recited in claim 7 , wherein the fins include two or more stacked nanosheets and the method includes patterning the nanosheets to form the fins, the nanosheets each including a semiconductor layer and the semiconductor layers are separated by a work function setting metal stack including a high dielectric constant layer; a diffusion prevention layer formed on the high dielectric constant layer; and an aluminum doped TiC layer having a thickness greater than 5 nm.
10 . The method as recited in claim 7 , wherein the diffusion prevention layer includes a TiN layer.
11 . The method as recited in claim 7 , wherein doping the TiC layer with aluminum includes providing an aluminum concentration of between about 20% and about 40%.
12 . The method as recited in claim 7 , wherein the gate dielectric layer includes a high dielectric constant layer.