Patent Assignment
Reel/Frame 073658/0439
Change of Name
Recorded: 2025-11-21
Pages: 8
Assignor
TESSERA, INC.
Executed: 2021-10-01
Assignee
TESSERA LLC
3025 ORCHARD PARKWAY, SAN JOSE, CALIFORNIA, 95134
Covered Properties
(100)
Method and Apparatus for Forming Nickel Silicide with Low Defect Density in Fet Devices
Increasing Electromigration Lifetime and Current Density in Ic Using Vertically Upwardly Extending Dummy Via
Method and Apparatus for Forming Nickel Silicide with Low Defect Density in Fet Devices
Low Resistance and Inductance Backside Through Vias and Methods of Fabricating Same
3D Integration Structure and Method Using Bonded Metal Planes
High-K/Metal Gate Mosfet with Reduced Parasitic Capacitance
Chip Guard Ring Including a Through-Substrate Via
Stack Packages Using Reconstituted Wafers
Integrated Structures of High Performance Active Devices and Passive Devices
Electrical Barrier Layers
Connector Structures and Methods
Hybrid Bonding Techniques for Multi-Layer Semiconductor Stacks
Integrated Structures of High Performance Active Devices and Passive Devices
Graphene and Metal Interconnects
Integrated Decoupling Capacitor Employing Conductive Through-Substrate Vias
Copper Wire and Dielectric with Air Gaps
Reliable Packaging and Interconnect Structures
Fin End Spacer for Preventing Merger of Raised Active Regions
Dielectric Liner for a Self-Aligned Contact via Structure
Sti Region for Small Fin Pitch in Finfet Devices
Method and Structure for Robust Finfet Replacement Metal Gate Integration
Finfet with Constrained Source-Drain Epitaxial Region
Reliable Packaging and Interconnect Structures
Heterogeneous Source Drain Region and Extension Region
Self-Aligned Quadruple Patterning Process
Dielectric Liner for a Self-Aligned Contact via Structure
Copper Wire and Dielectric with Air Gaps
Asymmetric High-K Dielectric for Reducing Gate Induced Drain Leakage
Graphene and Metal Interconnects with Reduced Contact Resistance
Optimized Wires for Resistance or Electromigration
Method of Forming Performance Optimized Gate Structures by Silicidizing Lowered Source and Drain Regions
Method of Forming Contact Useful in Replacement Metal Gate Processing and Related Semiconductor Structure
Patent:
9,337,094 →
Application:
14/589,222 →
Dual Work Function Integration for Stacked Finfet
Patent:
9,356,027 →
Application:
14/708,885 →
Sidewall Image Transfer Process for Fin Patterning
Patent:
9,287,135 →
Application:
14/721,430 →
Method to Form Stacked Germanium Nanowires and Stacked Iii-V Nanowires
Patent:
9,437,502 →
Application:
14/738,316 →
Semiconductor Fins for Finfet Devices and Sidewall Image Transfer (Sit) Processes for Manufacturing the Same
Insulating a via in a Semiconductor Substrate
Structure and Fabrication Method for Electromigration Immortal Nanoscale Interconnects
Patent:
9,418,934 →
Application:
14/754,999 →
Electrical Barrier Layers
Copper Wire and Dielectric with Air Gaps
Fin End Spacer for Preventing Merger of Raised Active Regions
Fin End Spacer for Preventing Merger of Raised Active Regions
Fin End Spacer for Preventing Merger of Raised Active Regions
Finfet with Constrained Source-Drain Epitaxial Region
Channel Strain and Controlling Lateral Epitaxial Growth of the Source and Drain in Finfet Devices
Patent:
9,431,486 →
Application:
14/953,851 →
Stress Retention in Fins of Fin Field-Effect Transistors
Interconnect Scaling Method Including Forming Dielectric Layer Over Subtractively Etched First Conductive Layer and Forming Second Conductive Material on Dielectric Layer
Patent:
9,502,350 →
Application:
15/009,108 →
Self-Aligned Quadruple Patterning Process
Channel Strain and Controlling Lateral Epitaxial Growth of the Source and Drain in Finfet Devices
Patent:
9,461,168 →
Application:
15/046,559 →
Performance Optimized Gate Structures Having Memory Device and Logic Device, the Memory Device with Silicided Source/Drain Regions That Are Raised with Respect to Silicided Source/Drain Regions of the Logic Device
Asymmetric High-K Dielectric for Reducing Gate Induced Drain Leakage
Asymmetric High-K Dielectric for Reducing Gate Induced Drain Leakage
Asymmetric High-K Dielectric for Reducing Gate Induced Drain Leakage
Asymmetric High-K Dielectric for Reducing Gate Induced Drain Leakage
Asymmetric High-K Dielectric for Reducing Gate Induced Drain Leakage
Dual Work Function Integration for Stacked Finfet
Dual Work Function Integration for Stacked Finfet
Asymmetric High-K Dielectric for Reducing Gate Induced Drain Leakage
Asymmetric High-K Dielectric for Reducing Gate Induced Drain Leakage
Interconnect Structure Having Subtractive Etch Feature and Damascene Feature
Patent:
9,601,426 →
Application:
15/166,570 →
Fin End Spacer for Preventing Merger of Raised Active Regions
Reliable Packaging and Interconnect Structures
Method for Wafer-Wafer Bonding
3D Bonded Semiconductor Structure with an Embedded Capacitor
Patent:
9,716,088 →
Application:
15/199,052 →
3D Bonded Semiconductor Structure with an Embedded Resistor
Patent:
9,620,479 →
Application:
15/199,129 →
Finfet with Constrained Source-Drain Epitaxial Region
Method of Forming Performance Optimized Gate Structures by Silicidizing Lowered Source and Drain Regions
Improving Channel Strain and Controlling Lateral Epitaxial Growth of the Source and Drain in Finfet Devices
Heterogeneous Source Drain Region and Extension Region
Optimized Wires for Resistance or Electromigration
Optimized Wires for Resistance or Electromigration
Systems and Methods for Producing Flat Surfaces in Interconnect Structures
Interconnect Structure Having Substractive Etch Feature and Damascene Feature
Asymmetric High-K Dielectric for Reducing Gate Induced Drain Leakage
Asymmetric High-K Dielectric for Reducing Gate Induced Drain Leakage
Semiconductor Fins for Finfet Devices and Sidewall Image Transfer (Sit) Processes for Manufacturing the Same
Semiconductor Fins for Finfet Devices and Sidewall Image Transfer (Sit) Processes for Manufacturing the Same
Semiconductor Fins for Finfet Devices and Sidewall Image Transfer (Sit) Processes for Manufacturing the Same
Reduction of Stress in via Structure
SEMICONDUCTOR DEVICE FORMED BY WET ETCH REMOVAL OF Ru SELECTIVE TO OTHER METALS
Patent:
10,090,247 →
Application:
15/585,704 →
Insulating a via in a Semiconductor Substrate
Reliable Packaging and Interconnect Structures
3D Bonded Semiconductor Structure with an Embedded Capacitor
Systems and Methods for Producing Flat Surfaces in Interconnect Structures
Integration of Super via Structure in Beol
Patent:
10,020,254 →
Application:
15/727,956 →
Asymmetric High-K Dielectric for Reducing Gate Induced Drain Leakage
Heterogeneous Source Drain Region and Extension Region
Asymmetric High-K Dielectric for Reducing Gate Induced Drain Leakage
Integration of Super via Structure in Beol
Patent:
10,020,255 →
Application:
15/798,794 →
Wet Etch Removal of Ru Selective to Other Metals
Asymmetric High-K Dielectric for Reducing Gate Induced Drain Leakage
Integration of Thick and Thin Nanosheet Transistors on a Single Chip
Patent:
10,229,971 →
Application:
15/815,061 →
Interconnect Structure Having Subtractive Etch Feature and Damascene Feature
Method of Forming a Three-Dimensional Bonded Semiconductor Structure Having Nitridized Oxide Regions
Homogeneous Densification of Fill Layers for Controlled Reveal of Vertical Fins
Systems and Methods for Producing Flat Surfaces in Interconnect Structures
Stress Retention in Fins of Fin Field-Effect Transistors
Reduction of Stress in via Structure
Asymmetric High-K Dielectric for Reducing Gate Induced Drain Leakage
Asymmetric High-K Dielectric for Reducing Gate Induced Drain Leakage
Related Assignments
(9)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Aug 26, 2013
From: KIM, TAE HONG; MCALLISTER, MICHAEL F.; SHAPIRO, MICHAEL J.; SPROGIS, EDMUND J.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 031081/0559 →
Assignment of Assignor's Interest
Nov 19, 2013
From: CHEN, FEN; GAMBINO, JEFFREY P.; HE, ZHONG-XIANG; THOMPSON, TREVOR A.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 031633/0014 →
Assignment of Assignor's Interest
Dec 4, 2013
From: UZOH, CYPRIAN EMEKA; HABA, BELGACEM; MITCHELL, CRAIG
To: TESSERA, INC.
Reel/Frame 031713/0188 →
Security Interest
Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
Assignment of Assignor's Interest
Jan 6, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: TESSERA, INC.
Reel/Frame 051489/0557 →
Assignment of Assignor's Interest
Jan 7, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: TESSERA, INC.
Reel/Frame 051493/0546 →
Security Interest
Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
Release of Security Interest
Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION
Reel/Frame 052920/0001 →
Change of Name
Nov 21, 2025
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 073658/0823 →