IP Library Granted Patent US 9,230,914
Granted Patent B2
US 9,230,914 · App. 14/526,741 · Granted Jan 5, 2016

Copper wire and dielectric with air gaps

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Quick Facts
Patent No.
US 9,230,914
App. No.
14/526,741
Granted
Jan 5, 2016
Kind
B2
Abstract

Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers.

Claims (50)

1. A semiconductor structure, comprising:

a dielectric layer with a via opening;

a wire comprising:

a barrier layer on and over the dielectric layer;

an electroplated material on and over the barrier layer;

a cap layer on and over the electroplated material; and

spacers on sidewalls of the electroplated material; and

a dielectric film over and around the wire and directly contacting a top surface of the cap layer, the spacers, and a top surface of the dielectric layer with the via opening,

wherein:

the barrier layer comprises a first conductive material;

the cap layer comprises a second conductive material different than the first conductive material; and

the spacers comprise an insulator material.

2. The semiconductor structure of claim 1 , further comprising:

a second wire; and

an air gap in the dielectric film between the wire and the second wire.

3. The semiconductor structure of claim 2 , wherein the second wire is on and contacting the barrier layer.

4. The semiconductor structure of claim 3 , wherein:

the second wire comprises a cap composed of a same material as the electroplated material; and

the second wire comprises sidewall spacers composed of a same material as the insulator material.

5. The semiconductor structure of claim 1 , wherein:

the first conductive material comprises Ti or TiN;

the second conductive material comprises Ni or CoWP; and

the electroplated material comprises copper.

6. The semiconductor structure of claim 1 , wherein the wire has sub-micron height and width.

7. The semiconductor structure of claim 1 , wherein the electroplated material directly contacts a via in the via opening.

8. The semiconductor structure of claim 7 , wherein the via electrically contacts another wire.

9. The semiconductor structure of claim 1 , further comprising a second wire on the barrier layer, wherein:

the wire and the second wire have a same height; and

a spacing between the wire and the second wire is less than the height.

10. The semiconductor structure of claim 9 , further comprising an air gap present in a dielectric material between the wire and the second wire.

11. The semiconductor structure of claim 1 , wherein a top surface of the spacers is at a same vertical level as a top surface of the cap layer.

12. A semiconductor structure, comprising:

a wire comprising:

a barrier layer;

an electroplated material on and over the barrier layer;

a cap layer on and over the electroplated material; and

spacers on sidewalls of the electroplated material,

wherein:

the barrier layer comprises a first conductive material;

the cap layer comprises a second conductive material different than the first conductive material;

the spacers comprise an insulator material; and

an uppermost top surface of the spacers is at a same horizontal plane as an uppermost top surface of the cap layer.

13. The semiconductor structure of claim 12 , wherein the cap layer comprises Ni (nickel) or CoWP (cobalt-tungsten-phosphide), and further comprising a dielectric film on and contacting the spacers and the cap layer.

14. The semiconductor structure of claim 13 , further comprising a dielectric layer with a via opening, and wherein:

the barrier layer is on and contacting the dielectric layer;

the barrier layer is in the via opening;

the dielectric film is on and contacting a top surface of the dielectric layer.

15. The semiconductor structure of claim 14 , further comprising:

a second wire on the barrier layer wherein: the wire and the second wire have a same height, and a spacing between the wire and the second wire is less than the height; and

an air gap in the dielectric film between the wire and the second wire.

Assignments (5)
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 073658/0439 →
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 073658/0823 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: TESSERA, INC.
Reel/Frame 051489/0557 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 29, 2014
From: CHEN, FEN; GAMBINO, JEFFREY P.; HE, ZHONG-XIANG; THOMPSON, TREVOR A.; WHITE, ERIC J.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 034061/0931 →