IP Library Granted Patent US 10,249,536
Granted Patent B2
US 10,249,536 · App. 15/464,007 · Granted Apr 2, 2019

Semiconductor fins for FinFET devices and sidewall image transfer (SIT) processes for manufacturing the same

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Quick Facts
Patent No.
US 10,249,536
App. No.
15/464,007
Granted
Apr 2, 2019
Kind
B2
Abstract

A method of forming a semiconductor structure includes providing a semiconductor substrate, forming at least one precursor semiconductor fin from the semiconductor substrate, etching through at least a portion of the at least one precursor semiconductor fin to form at least one patterned precursor semiconductor fin having a gap therein. The at least one patterned precursor semiconductor fin includes a first vertical surface and a second vertical surface with the gap therebetween. In addition, the method further includes forming a semiconductor material in the gap of the at least one patterned precursor semiconductor fin, in which the first vertical surface and the second vertical surface laterally surround the semiconductor material, and transforming the at least one patterned precursor semiconductor fin into at least one semiconductor fin including the semiconductor material therein.

Claims (24)

1. A semiconductor structure comprising:

a semiconductor substrate; and

at least one semiconductor fin disposed on the semiconductor substrate, wherein the at least one semiconductor fin includes an inner core comprising a silicon germanium (SiGe) material having a germanium content of from 10 atomic % to 90 atomic %, and an outer shell laterally surrounding the inner core of the at least one semiconductor fin, wherein the outer shell is composed of Si.

2. The semiconductor structure of claim 1 , wherein the outer shell has a height that is greater than a height of the inner core.

3. The semiconductor structure of claim 2 , further comprising a cap located on, and in direct physical contact with, a topmost surface of the inner core, the cap further comprising sidewalls physically contacting an upper portion of an inner sidewall of the outer core.

4. The semiconductor structure of claim 3 , wherein the cap has a topmost surface that is coplanar with a topmost surface of the outer core.

5. The semiconductor structure of claim 1 , wherein the germanium content of the silicon germanium material is from 20 atomic % to 90 atomic %.

6. The semiconductor structure of claim 2 , wherein bottommost surfaces of the inner core and outer shell are coplanar with each other and are in direct physical contact with a topmost surface of the semiconductor substrate.

7. The semiconductor structure of claim 2 , wherein an insulator layer is positioned between the semiconductor substrate and the at least one semiconductor fin, and wherein bottommost surfaces of the inner core and outer shell are coplanar with each other and are in direct physical contact with a topmost surface of the insulator material.

8. The semiconductor structure of claim 3 , wherein the sidewalls of the cap are vertically aligned with sidewalls of the inner core.

9. The semiconductor structure of claim 1 , further comprising a gate structure located on physically exposed surfaces of the at least one semiconductor fin.

10. The semiconductor structure of claim 1 , wherein the inner core has an epitaxial relationship with the outer shell.

11. A semiconductor structure comprising:

a semiconductor substrate; and

at least one semiconductor fin disposed on the semiconductor substrate, wherein the at least one semiconductor fin includes an inner core comprising a silicon germanium (SiGe) material having a germanium content of from 10 atomic % to 90 atomic %, and an outer shell laterally surrounding the inner core of the at least one semiconductor fin, wherein the outer shell is composed of SiGe having a germanium content of no greater than 10 atomic %.

12. The semiconductor structure of claim 11 , wherein the outer shell has a height that is greater than a height of the inner core.

13. The semiconductor structure of claim 12 , further comprising a cap located on, and in direct physical contact with, a topmost surface of the inner core, the cap further comprising sidewalls physically contacting an upper portion of an inner sidewall of the outer core.

14. The semiconductor structure of claim 13 , wherein the cap has a topmost surface that is coplanar with a topmost surface of the outer core.

15. The semiconductor structure of claim 11 , wherein the germanium content of the silicon germanium material is from 20 atomic % to 90 atomic %.

16. The semiconductor structure of claim 12 , wherein bottommost surfaces of the inner core and outer shell are coplanar with each other and are in direct physical contact with a topmost surface of the semiconductor substrate.

17. The semiconductor structure of claim 12 , wherein an insulator layer is positioned between the semiconductor substrate and the at least one semiconductor fin, and wherein bottommost surfaces of the inner core and outer shell are coplanar with each other and are in direct physical contact with a topmost surface of the insulator material.

18. The semiconductor structure of claim 13 , wherein the sidewalls of the cap are vertically aligned with sidewalls of the inner core.

19. The semiconductor structure of claim 11 , further comprising a gate structure located on physically exposed surfaces of the at least one semiconductor fin.

20. The semiconductor structure of claim 11 , wherein the inner core has an epitaxial relationship with the outer shell.

Assignments (5)
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 073658/0439 →
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 073658/0823 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: TESSERA, INC.
Reel/Frame 051489/0557 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 20, 2017
From: BASKER, VEERARAGHAVAN S.; CHENG, KANGGUO; STANDAERT, THEODORUS E.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 041648/0298 →