IP Library Granted Patent US 9,559,010
Granted Patent B2
US 9,559,010 · App. 15/075,944 · Granted Jan 31, 2017

Asymmetric high-k dielectric for reducing gate induced drain leakage

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Quick Facts
Patent No.
US 9,559,010
App. No.
15/075,944
Granted
Jan 31, 2017
Kind
B2
Abstract

An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

Claims (11)

1. A method comprising:

forming a gate first structure on a substrate on a gate dielectric material;

forming spacers on the gate first structure;

performing an angled implant on a source side of the gate first structure after spacer formation and after forming a mask on a drain side of the gate first structure to damage a region of the spacer on the source side only; and

performing a regrowth of oxygen on the drain side of the gate first structure to thicken a dielectric layer on the drain side of the gate first structure.

2. The method of claim 1 , wherein the damaged region on the source side is removed using etching processes, selective to the damaged region.

3. The method of claim 2 , further comprising forming a second spacer on exposed portions of the gate dielectric material, material of the gate first structure and spacer material remaining on the drain side.

4. The method of claim 3 , wherein the second spacer is a nitride material.

5. The method of claim 4 , further comprising removing horizontal surfaces of the spacer materials of the spacers and second spacer, and a cap material on the gate first structure.

6. The method of claim 5 , further comprising removing of the spacer material covering the gate dielectric material, formed on the drain side.

7. The method of claim 6 , wherein the growth process is a low temperature anneal process which forms a regrowth of oxygen on the drain side, while sidewalls on the source side will prevent or inhibit O 2 ingress during the anneal process.

Assignments (5)
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 073658/0439 →
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 073658/0823 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: TESSERA, INC.
Reel/Frame 051489/0557 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 21, 2016
From: CHOU, ANTHONY I.; KUMAR, ARVIND; LIN, CHUNG-HSUN; NARASIMHA, SHREESH; ORTOLLAND, CLAUDE; SHAW, JONATHAN T.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 038054/0546 →