IP Library Granted Patent US 10,381,452
Granted Patent B2
US 10,381,452 · App. 15/797,315 · Granted Aug 13, 2019

Asymmetric high-k dielectric for reducing gate induced drain leakage

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Quick Facts
Patent No.
US 10,381,452
App. No.
15/797,315
Granted
Aug 13, 2019
Kind
B2
Abstract

An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

Claims (15)

1. A gate structure comprising:

a dielectric layer on substrate, a source side and a drain side of the gate structure, the dielectric layer having a first thickness on the source side and a second thickness on the drain side to form a asymmetric gate dielectric;

sidewalls on gate material on the source side and the drain side; and

a high-k dielectric layer on the sidewalls on the drain side and underlying the gate material,

wherein the dielectric layer is an oxide layer on the drain side of the gate structure.

2. The gate structure of claim 1 , further comprising a nitridized high-k dielectric sidewall on the sidewalls on the source side of the gate structure.

3. The gate structure of claim 2 , wherein the nitridized sidewall inhibits oxide growth on the source side of the gate structure.

4. The gate structure of claim 2 , wherein the high-k dielectric sidewall is HfO 2 .

5. The gate structure of claim 1 , wherein the dielectric layer comprises nitrogen.

6. The gate structure of claim 1 , wherein the dielectric layer is composed of fin material under the high-k dielectric layer.

7. The gate structure of claim 1 , wherein the dielectric layer is thicker on the drain side of the gate structure than the source side of the gate structure.

8. The gate structure of claim 1 , wherein the high-k dielectric layer is directly on the oxide layer.

9. The gate structure of claim 8 , wherein the gate material is directly on the high-k dielectric layer.

10. The gate structure of claim 9 , wherein the gate material is a metal material.

11. The gate structure of claim 10 , wherein the metal material is TiN.

Assignments (5)
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 073658/0439 →
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 073658/0823 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: TESSERA, INC.
Reel/Frame 051489/0557 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 30, 2017
From: CHOU, ANTHONY I.; KUMAR, ARVIND; LIN, CHUNG-HSUN; NARASIMHA, SHREESH; ORTOLLAND, CLAUDE; SHAW, JONATHAN T.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 043983/0128 →