IP Library Granted Patent US 9,385,036
Granted Patent B2
US 9,385,036 · App. 14/329,744 · Granted Jul 5, 2016

Reliable packaging and interconnect structures

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Quick Facts
Patent No.
US 9,385,036
App. No.
14/329,744
Granted
Jul 5, 2016
Kind
B2
Abstract

Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.

Claims (35)

1. A method of manufacturing a structure comprising a semiconductor device, the method comprising:

forming a first opening in a substrate, the first opening extending down into the substrate;

forming a first feature for an interconnect structure, the first feature being electrically conductive and having a sidewall in the first opening; and

forming a second feature overlying the first feature and extending down into the first opening along the sidewall of the first feature, the second feature comprising a first material different from any material in the sidewall and top of the first feature.

2. The method of claim 1 further comprising:

forming a layer over the substrate and the first and second features; and

etching the layer to form a second opening exposing the second feature, the second feature serving as an etch stop during the etching.

3. The method of claim 2 further comprising forming an interconnect structure in the second opening.

4. The method of claim 1 wherein forming the first feature comprises:

forming a conductive layer in the first opening, the conductive layer comprising the first feature; and

removing a portion of the conductive layer to form the sidewall of the first feature.

5. The method of claim 4 wherein removing a portion of the conductive layer comprises:

oxidizing the portion of the conductive layer; and

removing the oxidized portion of the conductive layer to form the sidewall of the conductive layer.

6. The method of claim 1 wherein the second feature is conductive and physically contacts the first feature.

7. The method of claim 6 wherein the second feature comprises one or more of a group consisting of cobalt, nickel, tungsten, and phosphorus.

8. The method of claim 1 wherein the first opening passes through the substrate.

9. The method of claim 1 wherein the second feature has a thickness of 5 to 200 nm.

10. The method of claim 1 wherein the second feature covers at least 10% of the first feature's sidewall.

11. The method of claim 1 wherein the second feature covers at least 33% of the first feature's sidewall.

12. The method of claim 1 wherein the second feature is non-conductive.

13. A device comprising:

a substrate comprising a first opening extending down into the substrate;

a first feature which is electrically conductive and comprises at least a portion of an interconnect structure, the first feature having a sidewall in the first opening; and

a second feature overlying the first feature and extending down into the first opening along the sidewall of the first feature, the second feature comprising a first material different from any material in the sidewall and top of the first feature.

14. The device of claim 13 further comprising a third feature overlying the substrate and the first and second features;

wherein the third feature comprises a second opening extending down to the second feature, the second feature covering the first feature at a bottom of the second opening.

15. The device of claim 14 wherein the third feature is dielectric, and the device further comprises an interconnect structure in the second opening, the interconnect structure electrically contacting the first feature through the second feature.

16. The device of claim 13 wherein the second feature is conductive and physically contacts the first feature.

17. The device of claim 16 wherein the second feature comprises one or more of a group consisting of cobalt, nickel, tungsten, and phosphorus.

18. The device of claim 13 wherein the second feature is non-conductive and physically contacts the first feature.

19. The device of claim 13 wherein the first opening passes through the substrate.

20. The device of claim 13 wherein the second feature has a thickness of 5 to 200 nm.

21. The device of claim 13 wherein the second feature covers at least 10% of the first feature's sidewall.

22. The device of claim 13 wherein the second feature covers at least 33% of the first feature's sidewall.

Assignments (6)
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 073658/0439 →
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 073658/0823 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 11, 2014
From: UZOH, CYPRIAN EMEKA; HABA, BELGACEM; MITCHELL, CRAIG
To: TESSERA, INC.
Reel/Frame 033299/0904 →