IP Library Granted Patent US 9,543,213
Granted Patent B2
US 9,543,213 · App. 15/076,021 · Granted Jan 10, 2017

Asymmetric high-k dielectric for reducing gate induced drain leakage

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,543,213
App. No.
15/076,021
Granted
Jan 10, 2017
Kind
B2
Abstract

An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

Claims (15)

1. A method comprising:

performing a damaging process on a high-k dielectric sidewall of a gate structure;

performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region; and

removing the damaged high-k dielectric sidewall to expose underlying sidewalls on the source side, wherein the removing of the damaged high-k dielectric sidewall does not remove a sidewall on the gate structure on the drain side.

2. The method of claim 1 , wherein the sidewall is a high-k dielectric layer.

3. The method of claim 1 , wherein the damaging process is an implantation process.

4. The method of claim 3 , wherein the implantation process is an oxygen implant.

5. The method of claim 1 , wherein the damaging process is an implantation of a damaging species.

6. The method of claim 5 , wherein the damaging species includes one of Germanium, Xenon, and Argon.

7. The method of claim 1 , wherein the removing is a gentle etch removal process.

8. The method of claim 7 , wherein the gentle etch process is a dilute HF process, selective to the damaged sidewall.

9. The method of claim 1 , further comprises forming the gate structure within an opening between the sidewalls of the drain side and the source side.

10. The method of claim 9 , wherein the forming the gate structure is a deposition of metal materials.

11. The method of claim 10 , wherein the metal materials are of different work functions.

12. The method of claim 11 , wherein the oxygen annealing process is a low temperature O 2 anneal to regrow oxygen on the drain side of gate structure.

Assignments (5)
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 073658/0439 →
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 073658/0823 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: TESSERA, INC.
Reel/Frame 051489/0557 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 21, 2016
From: CHOU, ANTHONY I.; KUMAR, ARVIND; LIN, CHUNG-HSUN; NARASIMHA, SHREESH; ORTOLLAND, CLAUDE; SHAW, JONATHAN T.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 038054/0510 →