Reliable packaging and interconnect structures
View Patent ↗Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.
1. A semiconductor device, comprising:
a substrate;
an electrically conductive interconnect structure disposed on the substrate, wherein:
the electrically conductive interconnect structure partially extends within at least one trench in a dielectric region of the substrate; and
the electrically conductive interconnect structure has a top surface and at least one sidewall; and
a portion of the top surface of the at least one sidewall of the electrically conductive interconnect structure has been removed to create at least one gap between the at least one sidewall of the electrically conductive interconnect structure and at least one wall of the at least one trench; and
a dissimilar material disposed on and covering the top surface and a portion of the at least one side of the electrically conductive interconnect structure to at least partially fill the at least one gap.
2. The semiconductor device of claim 1 wherein the dissimilar material is conductive.
3. The semiconductor device of claim 1 wherein the dissimilar material is non-conductive.
4. The semiconductor device of claim 1 wherein the dissimilar material comprises a coupling layer.
5. The semiconductor device of claim 1 wherein the dissimilar material comprises an adhesion layer.
6. The semiconductor device of claim 1 wherein the dissimilar material comprises a conducting isolation layer.
7. The semiconductor device of claim 1 wherein the dissimilar material comprises a barrier layer.
8. The semiconductor device of claim 1 wherein the interconnect structure is a damascene structure.
9. The semiconductor device of claim 1 wherein the interconnect structure is a dual damascene structure.
10. The semiconductor device of claim 1 wherein the interconnect structure is a TSV structure.
11. The semiconductor device of claim 1 wherein the interconnect structure comprises copper.
12. The semiconductor device of claim 1 wherein the dissimilar material comprises a nano-metal.
13. The semiconductor device of claim 1 wherein the dissimilar material comprises CoP.
14. The semiconductor device of claim 1 wherein the dissimilar material comprises NiP.
15. The semiconductor device of claim 1 wherein the dissimilar material comprises NiW.
16. The semiconductor device of claim 1 wherein the dissimilar material has a grain size between 0.5 to 100 nm.
17. The semiconductor device of claim 1 wherein the dissimilar material has a thickness of between 2 to 500 nm.
18. The semiconductor device of claim 1 wherein the dissimilar material has a thickness of between 5 to 200 nm.
19. The semiconductor device of claim 1 further comprising a solderable material disposed on the dissimilar material.
20. The semiconductor device of claim 1 wherein the dissimilar material covers at least 10% of the at least one sidewall of the interconnect structure.
21. The semiconductor device of claim 1 wherein the dissimilar material covers at least 33% of the at least one sidewall of the interconnect structure.