Integration of thick and thin nanosheet transistors on a single chip
A method is presented for integrating a first nanosheet transistor and a second nanosheet transistor on a chip. The method includes constructing the first nanosheet transistor by forming a first nanosheet stack including alternating layers of a first material and a second material over a substrate, forming a dummy gate and first spacers over the first nanosheet stack, selectively etching the alternating layers of the first material to define gaps between the alternating layers of the second material, filling the gaps with second spacers, removing the dummy gate, removing a portion of the first nanosheet stack including layers of the first and second materials, and selectively removing remaining layers of the second material such that a single layer of the first material remains intact to define a single nanosheet channel. The method includes constructing the second nanosheet transistor by forming a second nanosheet stack having multiple layers of nanosheet channels.
1. A method for forming a first nanosheet transistor and a second nanosheet transistor, the method comprising:
constructing the first nanosheet transistor by:
forming a first nanosheet stack including alternating layers of a first material and a second material over a substrate;
forming a dummy gate and first spacers over the first nanosheet stack;
selectively etching the alternating layers of the first material to define gaps between the alternating layers of the second material;
filling the gaps with second spacers;
removing the dummy gate;
removing a portion of the first nanosheet stack including layers of the first and second materials; and
selectively removing remaining layers of the second material such that a single layer of the first material remains intact to define a single nanosheet channel; and
constructing the second nanosheet transistor by:
forming a second nanosheet stack having multiple layers of nanosheet channels.
2. The method of claim 1 , wherein the first nanosheet transistor is a thick oxide nanosheet transistor and the second nanosheet transistor is a thin oxide nanosheet transistor.
3. The method of claim 1 , wherein the first material is silicon germanium (SiGe) and the second material is silicon (Si).
4. The method of claim 1 , wherein a first dielectric layer is formed between the first nanosheet stack and the substrate.
5. The method of claim 4 , wherein the first dielectric layer is selectively etched to form a recess.
6. The method of claim 5 , wherein a second dielectric layer is deposited adjacent the single nanosheet channel and the recess.
7. The method of claim 1 , wherein the multiple layers of the second nanosheet stack are silicon (Si) layers.
8. The method of claim 7 , wherein a third dielectric is deposited adjacent each of the Si layers of the second nanosheet stack.
9. A method for forming a thick oxide nano sheet transistor and a thin oxide nanosheet transistor, the method comprising:
constructing the thick oxide nanosheet transistor by forming a first nanosheet stack by selectively removing alternating layers of first and second materials such that a single layer of the first material remains intact to define a single nanosheet channel; and
constructing the thin oxide nanosheet transistor by forming a second nanosheet stack having multiple layers of nanosheet channels.
10. The method of claim 9 , wherein the constructing of the thick oxide nanosheet transistor further includes:
forming a dummy gate and first spacers over the thick nanosheet stack; and
selectively etching the alternating layers of the first material to define gaps between the alternating layers of the second material.
11. The method of claim 10 , wherein the constructing of the thick oxide nanosheet transistor further includes:
filling the gaps with second spacers; and
removing the dummy gate before selectively removing the alternating layers of first and second materials.
12. A semiconductor structure, comprising:
a single nanosheet stack formed over a substrate;
a first nanosheet transistor formed by fabricating a first portion of the single nanosheet stack, the first nanosheet transistor having a single layer of nanosheet channel; and
a second nanosheet transistor formed by fabricating a second portion of the single nanosheet stack, the second nanosheet transistor having multiple layers of nanosheet channels.
13. The structure of claim 12 , wherein the first nanosheet transistor is a thick oxide nanosheet transistor and the second nanosheet transistor is a thin oxide nanosheet transistor.
14. The structure of claim 13 , wherein the single layer of nanosheet channel of the thick oxide nanosheet transistor includes a silicon (Si) layer.
15. The structure of claim 14 , wherein a thick gate oxide contacts opposed ends of the single layer of nanosheet channel of the thick oxide nanosheet transistor.
16. The structure of claim 15 , wherein a work function metal is deposited within a channel formed over the single layer of nanosheet channel of the thick oxide nanosheet transistor.
17. The structure of claim 13 , wherein the multiple layers of nanosheet channels of the thin oxide nanosheet transistor include Si layers.
18. The structure of claim 17 , wherein the Si layers are alternating layers defining the multiple layers of nanosheet channels of the thin oxide nanosheet transistor.
19. The structure of claim 18 , wherein a thin gate oxide contacts opposed ends of each of the multiple layers of the nanosheet channels of the thin oxide nanosheet transistor.
20. The structure of claim 19 , wherein a work function metal is deposited within a channel formed over the multiple layers of the nanosheet channels of the thin oxide nanosheet transistor.