Reduction of stress in via structure

1. A method for fabricating a via structure, the method comprising:

preparing a substrate having a top surface and a bottom surface opposite the top surface;

fabricating a via hole in the substrate from the top surface of the substrate to the bottom surface of the substrate;

disposing a stress buffer layer on the top surface of the substrate, the stress buffer layer having an opening aligned to the via hole of the substrate; and

filling the via hole with a conductive material from the bottom surface of the substrate at least up to the top surface of the substrate, the stress buffer layer reducing stress generated due to coefficient of thermal expansion mismatch associated with the via hole and the substrate;

wherein the conductive material extends into the opening above the top surface of the substrate and/or covers, at least in part, an edge of the top surface of the substrate around the via hole.

2. The method of claim 1 , wherein the method further comprises:

disposing a metal material on the stress buffer layer and the conductive material; and

disposing a polymer dielectric layer over the metal material to forma redistribution layer on the substrate, the redistribution layer being composed of the stress buffer layer, the metal material and the polymer dielectric layer.

3. The method of claim 2 , wherein the method further comprises:

forming a bump on the metal material, the bump including a metal post and/or a solder, the bump being electrically connected with the conductive material filled in the via hole through the metal material.

4. The method of claim 1 , wherein the filling further comprises:

forming a bump by using the conductive material above the via hole.

5. The method of claim 1 , wherein the substrate has a pad wiring to the via hole on the first surface and the stress buffer layer has a second opening aligned to the pad on the substrate, the method further comprising:

disposing a polymer dielectric layer over the conductive material filled in the via hole and the stress buffer layer to form a redistribution layer on the substrate, the redistribution layer being composed of the stress buffer layer and the polymer dielectric layer;

forming a hump on the pad of the substrate, the bump being electrically connected with the conductive material filled in the via hole through the pad.

6. The method of claim 5 , wherein the filling comprises filling the second opening with the conductive material, the forming comprises forming the bump by way of the conductive material filled in the second opening.

7. The method of claim 1 , wherein the substrate has further a second surface, the via hole is a through hole penetrating through the substrate from the first surface to the second surface, and the method further comprises:

forming a second stress buffer layer on the second surface of the substrate, the second stress buffer layer having an opening aligned to the via hole of the substrate;

wherein the second stress buffer layer receives the conductive material extending into the opening over the level of the second surface of the substrate and/or covers, at least in part, the edge of the second surface around the via hole of the substrate.

8. The method of claim 1 , wherein the substrate is made of a glass or silicon, the stress buffer layer is made of polymer dielectric and the filling comprises:

filling the via hole with a solder by Injection Molded Solder (IMS) technology.

9. The method of claim 1 , wherein the preparing comprises:

stacking a plurality of substrate layers as the substrate; and

penetrating through at least one of the substrate layers from the first surface to form the via hole of the substrate.

10. A method for fabricating a via structure, the method comprising:

preparing a substrate having a top surface and a bottom surface opposite the top surface, a via hole in the substrate from the top surface of the substrate to the bottom surface of the substrate, and a stress buffer layer disposed on the top surface of the substrate, the stress buffer layer having an opening aligned to the via hole and reducing stress generated due to coefficient of thermal expansion mismatch associated with the via hole and the substrate; and

forming, in the via hole, a conductive body having a protrusion part extending into the opening of the stress buffer layer above the top surface of the substrate.

11. The method of claim 10 , wherein the method further comprises:

disposing a metal material on the stress buffer layer and the conductive body; and

disposing a polymer dielectric layer over the metal material to form a redistribution layer on the substrate, the redistribution layer being composed of the stress buffer layer, the metal material and the polymer dielectric layer.

12. The method of claim 2 , further comprising forming a second redistribution layer on the bottom surface of the substrate.

13. The method of claim 12 , wherein forming the second redistribution layer further comprises disposing a metal material on the bottom surface of the substrate.

14. The method of claim 13 , wherein forming the second redistribution layer further comprises disposing a polymer dielectric material on the metal material.

15. The method of claim 11 , wherein the method further comprises:

forming a bump on the metal material, the bump including a metal post and/or a solder, the bump being electrically connected with the conductive material filled in the via hole through the metal material.

16. The method of claim 11 , further comprising forming a second redistribution layer on the bottom surface of the substrate.

17. The method of claim 16 , wherein forming the second redistribution layer further comprises disposing a metal material on the bottom surface of the substrate.

18. The method of claim 16 , wherein forming the second redistribution layer further comprises disposing a polymer dielectric material on the metal material.