Integration of super via structure in BEOL
View Patent ↗Semiconductor devices including super via structures and BEOL processes for forming the same, according to embodiments of the invention, generally include removing selected portions of a nitride cap layer intermediate interconnect levels, wherein the selected portions correspond to the regions where the super via structure is to be formed and where underlying overlay alignment markers are located.
1. A process of fabricating a semiconductor device including a super via interconnect structure, the process comprising:
providing a structure including a first interconnect level, a second interconnect level, a first nitride cap layer intermediate the first and second interconnect levels, and a second nitride cap on the second interconnect level;
removing selected portions of the second nitride cap layer to expose portions of a dielectric material in the second interconnect level, wherein underlying the exposed portions of the dielectric material in the second interconnect level comprise a first metal conductor and a metal alignment marker;
depositing a layer of dielectric material onto the second interconnect level to form a third interconnect level, wherein the dielectric material in the third interconnect level is the same as the dielectric material in the second interconnect level;
patterning the layer of dielectric material in the third interconnect level to form via structures spanning the third interconnect level to the metal conductor and the metal alignment marker in the second interconnect level and patterning the layer of dielectric material in the third interconnect level and the layer of dielectric material in the second interconnect level to form a super via structure to the metal conductor in the first interconnect level; and
filling the super via structure and the via structures with a metal conductor.
2. The process of claim 1 , wherein patterning the layer of dielectric material in the third interconnect level and patterning the layer of dielectric material in the third interconnect level and the layer of dielectric material in the second interconnect level is simultaneous.
3. The process of claim 1 , wherein the metal conductor is copper.
4. The process of claim 1 , wherein the nitride cap layer is silicon nitride.
5. The process of claim 1 , wherein patterning the layer of dielectric material in the third interconnect level and patterning the layer of dielectric material in the third interconnect level and the layer of dielectric material in the second interconnect level comprises depositing a hard mask onto the third interconnect level comprising titanium nitride and silicon nitride; removing selected portions of the hardmask; and reactive ion etching to form the via structures and the at least one super via structure.
6. The process of claim 1 , further comprising treating a surface of the exposed portions of the dielectric material in the second interconnect level.
7. The process of claim 6 , wherein treating the surface comprises exposing the surface to plasma, ozone, ultraviolet light, or combinations thereof for an amount effective to increase adhesion of the third interconnect level to the exposed portions of the dielectric material in the second interconnect level.
8. A semiconductor device including a super via structure, the device comprising:
a plurality of interconnect levels comprising a metal conductor formed in a dielectric layer, wherein each of the interconnect levels is separated from an adjacent interconnect level with a nitride cap layer
a plurality of via structures formed electrically couple the metal conductor in a selected interconnect level with the metal conductor in the adjacent interconnect level; and
at least one super via structure spans two of the plurality of interconnect levels without a landing pad on an intermediate interconnect level, wherein the at least one super via structure is free of a necking profile, has a height that is twice that of the via structure, and has a tapered profile the same as the via structure.