Asymmetric high-k dielectric for reducing gate induced drain leakage
View Patent ↗An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
1. A method, comprising:
performing a blocking process on a high-k dielectric sidewall on a source side of a gate structure; and
performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on the source side of the gate structure adjacent to a source region,
wherein the blocking process is a damaging implant process, which damages the high-k dielectric sidewall on the source side of the gate structure, and further comprising removing the damaged sidewall prior to performing the oxygen annealing process, and
wherein the gate structure is a finFET gate.
2. The method of claim 1 , wherein the blocking process comprises deposition of a masking material overlapping the source side of the gate structure.
3. The method of claim 2 , wherein the masking material is a nitrogen material.
4. The method of claim 1 , wherein the oxygen annealing process is a low temperature oxygen anneal.
5. The method of claim 4 , wherein the low temperature oxygen anneal is at 500° C. for about 30 minutes.
6. A method, comprising:
performing a blocking process on a high-k dielectric sidewall on a source side of a gate structure; and
performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on the source side of the gate structure adjacent to a source region,
wherein the blocking process is a damaging implant process, which damages the high-k dielectric sidewall on the source side of the gate structure, and further comprising removing the damaged sidewall prior to performing the oxygen annealing process, and
wherein the gate structure is a planar gate.
7. A method, comprising:
performing a blocking process on a high-k dielectric sidewall on a source side of a gate structure; and
performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on the source side of the gate structure adjacent to a source region,
wherein the blocking process is a damaging implant process, which damages the high-k dielectric sidewall on the source side of the gate structure, and further comprising removing the damaged sidewall prior to performing the oxygen annealing process,
wherein the blocking process comprises deposition of a masking material overlapping the source side of the gate structure, and
wherein oxygen is prevented from channeling into a substrate via the high-k dielectric on the sidewall on the source side.
8. The method of claim 7 , wherein the high-k dielectric on the sidewall is composed of HfO 2 .