Reduction of stress in via structure
A via structure for electric connection is disclosed. The via structure includes a substrate that has a first surface and a via hole opened to the first surface. The via structure includes also a stress buffer layer disposed on the first surface of the substrate, which has an opening aligned to the via hole of the substrate. The via structure further includes a conductive body formed in the via hole of the substrate at least up to the level of the first surface of the substrate. In the via structure, the stress buffer layer receives the conductive body extending into the opening over the level of the first surface of the substrate and/or covers, at least in part, the edge of the first surface around the via hole of the substrate.
1. A via structure for electric connection, the via structure comprising:
a substrate having a plurality of stacked substrate layers, a first surface and a via hole penetrating through the first surface of the substrate to an electrode within a first one of the substrate layers;
a stress buffer layer disposed on the first surface of the substrate, the stress buffer layer having an opening aligned to the via hole of the substrate and including a stress reduction material configured to reduce stress generated due to coefficient of thermal expansion mismatch associated with the via hole and the substrate; and
a conductive body formed in the via hole of the substrate at least up to the level of the first surface of the substrate;
wherein the stress buffer layer receives the conductive body extending into the opening over the level of the first surface of the substrate and/or covers, at least in part, the edge of the first surface around the via hole of the substrate.
2. The via structure of claim 1 , wherein the substrate is made of a glass or silicon, the stress buffer layer is made of a polymer dielectric and the conductive body is made of a solder.
3. The via structure of claim 1 , wherein the via structure further comprises:
a wiring layer disposed on the stress buffer layer and the conductive body; and
a polymer dielectric layer disposed over the wiring layer, the polymer dielectric layer constituting a redistribution layer on the substrate together with the stress buffer layer and the wiring layer.
4. The via structure of claim 3 , wherein the via structure further comprises:
a bump formed on the wiring layer, the bump including a metal post and/or a solder, the bump being electrically connected with the conductive body through the wiring layer.
5. The via structure of claim 3 , wherein the polymer dielectric layer includes a permanent resist.
6. The via structure of claim 1 , wherein the conductive body forms a bump above the via hole.
7. The via structure of claim 1 , wherein the stress buffer layer includes a permanent resist.
8. The via structure of claim 1 , wherein the substrate has a pad wiring to the via hole on the first surface and the stress buffer layer has a second opening aligned to the pad on the substrate, the via structure further comprising:
a polymer dielectric layer disposed over the conductive body in the via hole and the stress buffer layer, the polymer dielectric layer constituting a redistribution layer on the substrate together with the stress buffer layer; and
a bump formed on the pad of the substrate, the bump being electrically connected with the conductive body in the via hole through the pad.
9. The via structure of claim 1 , wherein the substrate has further a second surface and the via hole is a through hole penetrating through the substrate from the first surface to the second surface.
10. An electronic apparatus, wherein the electronic apparatus has a via structure, the via structure comprising:
a substrate having a plurality of stacked substrate layers, a first surface and a via hole penetrating through the first surface of the substrate to an electrode within a first one of the substrate layers;
a stress buffer layer disposed on the first surface of the substrate, the stress buffer layer having an opening aligned to the via hole of the substrate and including a stress reduction material configured to reduce stress generated due to coefficient of thermal expansion mismatch associated with the via hole and the substrate; and
a conductive body formed in the via hole of the substrate at least up to the level of the first surface of the substrate;
wherein the stress buffer layer receives the conductive body extending into the opening over the level of the first surface of the substrate and/or covers, at least in part, the edge of the first surface around the via hole of the substrate.
11. The electronic apparatus of claim 10 , wherein the substrate is made of a glass or silicon, the stress buffer layer is made of a polymer dielectric and the conductive body is made of a solder.
12. The electronic apparatus of claim 10 , wherein the via structure further comprises:
a wiring layer disposed on the stress buffer layer and the conductive body;
a polymer dielectric layer disposed over the wiring layer, the polymer dielectric layer constituting a redistribution layer on the substrate together with the stress buffer layer and the wiring layer; and
a bump formed on the wiring layer, the bump including a metal post and/or a solder, the bump being electrically connected with the conductive body through the wiring layer.
13. The electronic apparatus of claim 12 , wherein the polymer dielectric layer includes a permanent resist.
14. The electronic apparatus of claim 10 , wherein the conductive body forms a bump above the via hole.
15. The electronic apparatus of claim 10 , wherein the stress buffer layer includes a permanent resist.
16. The electronic apparatus of claim 10 , wherein the substrate has a pad wiring to the via hole on the first surface and the stress buffer layer has a second opening aligned to the pad on the substrate, the via structure further comprising:
a polymer dielectric layer disposed over the conductive body in the via hole and the stress buffer layer, the polymer dielectric layer constituting a redistribution layer on the substrate together with the stress buffer layer; and
a bump formed on the pad of the substrate, the bump being electrically connected with the conductive body in the via hole through the pad.
17. The via structure of claim 1 , wherein the conductive body has a staircase shaped geometry.
18. The via structure of claim 1 , wherein the plurality of stacked substrate layers each include an electrode, and the conductive body is in contact with each electrode.
19. The electronic apparatus of claim 10 , wherein the conductive body has a staircase shaped geometry.
20. The electronic apparatus of claim 10 , wherein the plurality of stacked substrate layers each include an electrode, and the conductive body is in contact with each electrode.