Chip guard ring including a through-substrate via
View Patent ↗At least one through-substrate via is formed around the periphery of a semiconductor chip or a semiconductor chiplet included in a semiconductor chip. The at least one through-substrate via may be a single through-substrate via that laterally surrounds the semiconductor chip or the semiconductor chiplet, or may comprise a plurality of through-substrate vias that surrounds the periphery with at least one gap among the through-substrate vias. A stack of back-end-of-line (BEOL) metal structures that laterally surrounds the semiconductor chip or the semiconductor chiplet are formed directly on the substrate contact vias and electrically connected to the at least one through-substrate via. A metallic layer is formed on the backside of the semiconductor substrate including the at least one through-substrate via. The conductive structure including the metallic layer, the at least one through-substrate via, and the stack of the BEOL metal structures function as an electrical ground built into the semiconductor chip.
1. A semiconductor structure comprising:
a semiconductor device located on a semiconductor substrate;
at least one through-substrate via extending from a bottom surface of said semiconductor substrate and at least to a top surface of said semiconductor substrate and located within a peripheral region of said semiconductor substrate;
at least one dielectric material layer located on said semiconductor device and embedding at least one metal interconnect structure;
a metallic enclosure structure laterally surrounding and enclosing an inner portion of said at least one dielectric material layer and vertically abutting a top surface of said at least one through-substrate via; and
a metallic layer vertically abutting a bottom surface of said at least one through-substrate via and a bottom surface of said semiconductor substrate.
2. The semiconductor structure of claim 1 , further comprising at least one substrate contact via abutting a top surface of said semiconductor substrate and a bottom surface of said metal enclosure structure.
3. The semiconductor structure of claim 2 , further comprising at least one doped semiconductor well located in said semiconductor substrate and vertically contacting said at least one substrate contact via.
4. The semiconductor structure of claim 2 , wherein said at least one through-substrate via is a single through-substrate via of unitary and integral construction that laterally surrounds and laterally encloses an inner portion of said semiconductor substrate and is resistively connected to said at least one substrate contact via through said metallic enclosure structure.
5. The semiconductor structure of claim 1 , wherein said at least one through-substrate via is embedded in said semiconductor substrate, wherein said semiconductor substrate is a bulk substrate, a semiconductor-on-insulator (SOI) substrate, or a hybrid substrate having a bulk portion and a semiconductor-on-insulator portion, and wherein said at least one through-substrate via comprises an elemental metal, an intermetallic alloy, a conductive metal nitride, a conductive metal-semiconductor alloy, or a doped semiconductor material.
6. The semiconductor structure of claim 1 , wherein an outer portion of at least one dielectric material layer laterally surrounds and encloses said metallic enclosure structure.
7. The semiconductor structure of claim 6 , wherein said metallic enclosure structure is a single contiguous structure extending from a top surface of said at least one through-substrate via to a topmost surface of said at least one dielectric material layer, wherein said inner portion of said at least one dielectric material layer is separated from, and does not abut, said outer portion of said at least one dielectric material layer.
8. The semiconductor structure of claim 1 , wherein said at least one metal interconnect structure includes at least one metal pad having an exposed top surface that is substantially coplanar with a topmost surface of said metallic enclosure structure.
9. The semiconductor structure of claim 8 , wherein said at least one through-substrate via is not electrically wired to said at least one metal pad through any metal interconnect structure in said at least one dielectric material layer.
10. The semiconductor structure of claim 8 , wherein said at least one through-substrate via is electrically wired to said at least one metal pad through said at least one metal interconnect structure in said at least one dielectric material layer.
11. The semiconductor structure of claim 1 , wherein said at least one through-substrate via is a plurality of through-substrate vias.
12. The semiconductor structure of claim 1 , wherein said at least one through-substrate via laterally abuts said semiconductor substrate.
13. A method of forming a semiconductor structure comprising:
forming at least one through-substrate via and at least one substrate contact via within a peripheral region of a semiconductor substrate;
forming at least one dielectric material layer and at least one metal interconnect structure embedded therein on said semiconductor substrate;
forming a metallic enclosure structure directly on a top surface of said at least one through-substrate via, wherein said metallic enclosure structure laterally surrounds and encloses an inner portion of said at least one dielectric material layer; and
forming a metallic layer directly on a bottom surface of said at least one through-substrate via and a bottom surface of said semiconductor substrate.
14. The method of claim 13 , wherein said at least one through-substrate via is a single through-substrate via of unitary and integral construction that laterally surrounds and laterally encloses said semiconductor substrate.
15. The method of claim 13 , wherein said metallic enclosure structure is a single contiguous structure extending from a top surface of said at least one through-substrate via to a topmost surface of said at least one dielectric material layer, and wherein an inner portion of said at least one dielectric material layer is separated from, and does not abut, an outer portion of said at least one dielectric material layer.
16. The method of claim 13 , further comprising forming at least one metal pad having an exposed top surface that is substantially coplanar with a topmost surface of said metallic enclosure structure.
17. The method of claim 16 , wherein said at least one through-substrate via is not electrically wired to said at least one metal pad through any metal interconnect structure in said at least one dielectric material layer.
18. The method of claim 16 , wherein said at least one through-substrate via is electrically wired to said at least one metal pad through said at least one metal interconnect structure in said at least one dielectric material layer.
19. The method of claim 13 , further comprising removing a bottom portion of said semiconductor substrate and exposing said bottom surface of said at least one through-substrate via prior to forming said metallic layer.
20. The method of claim 13 , further comprising forming at least one semiconductor device on said semiconductor substrate, wherein said at least one semiconductor device is electrically grounded through said at least one substrate contact via, said metallic enclosure structure, and said at least one through-substrate via to said metallic layer, and wherein said metallic layer is electrically grounded during packaging of a semiconductor chip including said semiconductor substrate.