Dual work function integration for stacked FinFET
A three-dimensional stacked fin complementary metal oxide semiconductor (CMOS) device having dual work function metal gate structures is provided. The stacked fin CMOS device includes a fin stack having a first semiconductor fin over a substrate, a dielectric fin atop the first semiconductor fin and a second semiconductor fin atop the dielectric fin, and a gate sack straddling the fin stack. The gate stack includes a first metal gate portion surrounding a channel portion of the first semiconductor fin and a second metal gate portion surrounding a channel portion of the second semiconductor fin. The first metal gate portion has a first work function suitable to reduce a threshold voltage of a field effect transistor (FET) of a first conductivity type, while the second gate portion has a second work function suitable to reduce a threshold voltage of a FET of a second conductivity type opposite the first conductivity type.
1. A semiconductor structure comprising:
at least one fin stack located on a substrate, the at least one fin stack comprising a first semiconductor fin, a dielectric fin atop the first semiconductor fin, and a second semiconductor fin atop the dielectric fin; and
at least one gate stack straddling a portion of the at least one fin stack, the at least one gate stack comprising:
a gate dielectric, the gate dielectric contacting a channel portion of the first semiconductor fin, a portion of the dielectric fin, and a channel portion of the second semiconductor fin;
a first work function metal portion overlying a lower portion of the gate dielectric, the first work function metal portion surrounding the channel portion of the first semiconductor fin;
a first gate conductor overlying the first work function metal portion;
a second work function metal overlying a remaining portion of the gate dielectric, the first work function metal portion and the first gate conductor, the second work function metal surrounding the channel portion of the second semiconductor fin; and
a second gate conductor overlying the second work function metal.
2. The semiconductor structure of claim 1 , wherein the first work function metal portion and the first gate conductor surround a lower portion of the portion of the dielectric fin, and the second work function metal and the second gate conductor surround a remaining portion of the portion of the dielectric fin.
3. The semiconductor structure of claim 1 , wherein each of the first work function metal portion and the first gate conductor has a top surface located between a top surface of the dielectric fin and a bottom surface of the dielectric fin.
4. The semiconductor structure of claim 1 , wherein the first work function metal portion has a first work function, and the second work function metal has a second work function different from the first work function.
5. The semiconductor structure of claim 4 , wherein one of the first work function metal portion and the second work function metal has a work function ranging from 4.1 eV to 4.3 eV, and another of the first work function metal portion and the second work function metal has a work function ranging from 4.5 eV to 5.2 eV.
6. The semiconductor structure of claim 4 , wherein one of the first work function metal portion and the second work function metal comprises TiAlC, TaAlC, TiAl, Ti or Al, and another of the first work function metal portion and the second work function metal comprises TiN, TaN, NbN, VN or WN.
7. The semiconductor structure of claim 1 , wherein the first work function metal portion is in contact with the lower portion of the gate dielectric, and the second work function metal is in contact with an upper portion of the gate dielectric.
8. The semiconductor structure of claim 1 , wherein a topmost surface of the first gate conductor is coplanar with a topmost surface of the first work function metal portion.
9. The semiconductor structure of claim 1 , further comprising an ILD layer laterally surrounding the second work function metal and the second gate conductor, wherein topmost surfaces of each of the gate dielectric, the second work function metal and the second gate conductor are coplanar with a topmost surface of the ILD layer.
10. The semiconductor structure of claim 1 , further comprising first source/drain regions in portions of the first semiconductor fin on opposite sides of the gate stack, and second source/drain regions in portions of the second semiconductor fin on opposite sides of the gate stack, wherein the first source/drain regions comprises dopants of a first conductivity type, and the second source/drain regions comprises dopants of a second conductivity type opposite the first conductivity type.
11. The semiconductor structure of claim 10 , further comprising a contact structure that connects one of the first source/drain regions to one of the second source/drain regions.
12. The semiconductor structure of claim 1 , wherein the first semiconductor fin comprises a silicon material, and the second semiconductor fin comprises a silicon germanium material.
13. The semiconductor structure of claim 1 , wherein the dielectric fin comprises silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.