FinFET with constrained source-drain epitaxial region
View Patent ↗A method includes forming a plurality of fins on a substrate, conformally depositing a nitride liner above and in direct contact with the plurality of fins and the substrate, removing a top portion of the nitride liner above the plurality of fins to expose a top surface of the plurality of fins, forming a gate over a first portion of the plurality of fins, a second portion of the plurality of fins remains exposed, forming spacers on opposite sidewalls of the nitride liner on the second portion of the plurality of fins, removing the second portion of the plurality of fins to form a trench between opposing sidewalls of the nitride liner, and forming an epitaxial layer in the trench, the lateral growth of the epitaxial layer is constrained by the nitride liner to form constrained source-drain regions.
1. A method comprising:
forming a plurality of fins on a substrate;
conformally depositing a nitride liner above and in direct contact with the plurality of fins and the substrate;
removing a top portion of the nitride liner above the plurality of fins to expose a top surface of the plurality of fins;
forming a gate over a first portion of the plurality of fins, a second portion of the plurality of fins remains exposed;
forming spacers on opposite sidewalls of the nitride liner on the second portion of the plurality of fins;
removing the second portion of the plurality of fins to form a trench between opposing sidewalls of the nitride liner; and
forming an epitaxial layer in the trench, wherein lateral growth of the epitaxial layer is constrained by the nitride liner to form constrained source-drain regions.
2. The method of claim 1 , further comprising:
depositing a dielectric layer above the nitride liner;
polishing the dielectric layer to expose a top portion of the nitride liner; and
removing the dielectric layer.
3. The method of claim 1 , wherein forming the epitaxial layer comprises:
epitaxially growing an in-situ doped semiconductor material including silicon or silicon-germanium.
4. The method of claim 1 , wherein the substrate comprises a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate.
5. The method of claim 1 , wherein removing the second portion of the plurality of fins to form the trench between the spacers comprises:
removing an upper region of the second portion of the plurality of fins while a lower region of the second portion of the plurality of fins remains in the trench,
wherein the lower region of the second portion of the plurality of fins provides a seed for growing the epitaxial layer on SOI substrates.
6. The method of claim 1 , further comprising:
forming an extended epitaxial region directly on top of the epitaxial layer and above the trench.
7. The method of claim 6 , wherein the extended epitaxial region comprises epitaxial growth on a {111} plane.
8. The method of claim 6 , wherein the extended epitaxial region comprises a triangular shape.
9. A structure comprising:
a plurality of fins on a substrate;
a gate over a first portion of the plurality of fins, wherein a second portion of the plurality of fins not covered by the gate comprises an epitaxial layer geometrically constrained by a pair of spacers located on opposite sidewalls of the second portion of the plurality of fins; and
a nitride liner located between the pair of spacers and the second portion of the plurality of fins, wherein the nitride liner further constrains the second portion of the plurality of fins.
10. The structure of claim 9 , wherein the epitaxial layer comprises an in-situ doped semiconductor material.
11. The structure of claim 9 , wherein the nitride liner comprises an etch stop to prevent over etch of substrate areas located between the plurality of fins.
12. The structure of claim 9 , further comprising:
an extended epitaxial region directly on top of the epitaxial layer, wherein the extended epitaxial region has a triangular shape.