IP Library Granted Patent US 10,090,247
Granted Patent B1
US 10,090,247 · App. 15/585,704 · Granted Oct 2, 2018

Semiconductor device formed by wet etch removal of Ru selective to other metals

Inventors: Benjamin D. Briggs (Waterford, NY); Cornelius B. Peethala (Albany, NY); David L. Rath (Stormville, NY)
Assignee: International Business Machines Corporation
H01L23/53238H01L21/32134H01L21/76847
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Quick Facts
Patent No.
US 10,090,247
App. No.
15/585,704
Granted
Oct 2, 2018
Kind
B1
Abstract

A method for forming a conductive structure for a semiconductor device includes depositing a barrier layer in a trench formed in a dielectric material and forming an interface layer over the barrier layer. A main conductor is formed over the interface layer, and the main conductor is recessed selectively to the interface layer and the barrier layer to a position below a top surface of the dielectric layer. The interface layer is selectively wet etched to the main conductor and the barrier layer using a chemical composition having an oxidizer, wherein the chemical composition is buffered to include a pH above 7. The barrier layer is selectively etching to the main conductor and the interface layer.

Claims (31)

1. A semiconductor device, comprising:

a substrate including semiconductor components;

a dielectric layer formed over the substrate;

a barrier layer formed in a trench formed in the dielectric layer;

a ruthenium (Ru) interface layer formed over the barrier layer;

a main conductor formed over the interface layer;

a recess formed by recessing the barrier layer, the interface layer and the main conductor in the trench below a top surface of the dielectric layer, wherein the barrier layer is recessed to a same level as a common surface of the main conductor and the interface layer; and

a conductive structure contacting the main conductor, the conductive structure including a second ruthenium (Ru) interface layer.

2. The device as recited in claim 1 , wherein the recess is filled with a conductive material to form a self-aligned conductor.

3. The device as recited in claim 1 , wherein the barrier layer includes TaN and the main conductor includes Cu.

4. The device as recited in claim 1 , wherein the conductive structure further includes a second barrier layer formed in a second trench that includes the recess, and wherein the second interface layer is formed over the second barrier layer.

5. The device as recited in claim 4 , wherein the second trench is formed to the common surface.

6. The device as recited in claim 4 , wherein the second trench is formed in a second dielectric layer formed on the substrate.

7. The device as recited in claim 4 , wherein the conductive structure further includes a second dielectric layer conformally formed on the second barrier layer.

8. The device as recited in claim 1 , wherein the conductive structure further includes a second main conductor formed over the second interface layer.

9. A semiconductor device, comprising:

a substrate including semiconductor components;

a dielectric layer formed over the substrate;

a barrier layer formed in a trench formed in the dielectric layer;

a ruthenium (Ru) interface layer formed over the barrier layer;

a main conductor formed over the interface layer;

a recess formed by recessing the barrier layer, the interface layer and the main conductor in the trench below a top surface of the dielectric layer, wherein the barrier layer is recessed to a same level as a common surface of the main conductor and the interface layer; and

a conductive structure contacting the main conductor, the conductive structure including:

a second barrier layer formed in a second trench that includes the recess;

a second ruthenium (Ru) interface layer formed over the second barrier layer; and

a second main conductor formed over the second interface layer.

10. The device as recited in claim 9 , wherein the recess is filled with a conductive material to form a self-aligned conductor.

11. The device as recited in claim 9 , wherein the barrier layer includes TaN and the main conductor includes Cu.

12. The device as recited in claim 9 , wherein the second trench is formed to the common surface.

13. The device as recited in claim 9 , wherein the second trench is formed in a second dielectric layer formed on the substrate.

14. The device as recited in claim 13 , wherein the conductive structure further includes a third dielectric layer conformally formed on the second barrier layer.

Assignments (5)
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 073658/0439 →
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 073658/0823 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 7, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: TESSERA, INC.
Reel/Frame 051493/0546 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 3, 2017
From: BRIGGS, BENJAMIN D.; PEETHALA, CORNELIUS B.; RATH, DAVID L.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 042227/0400 →
Cited By (2)
US 12,557,631 US 12,598,970