Channel strain and controlling lateral epitaxial growth of the source and drain in FinFET devices
View Patent ↗A multi-gate finFET structure and formation thereof. The multi-gate finFET structure has a first gate structure that includes an inner side and an outer side. Adjacent to the first gate structure is a second gate structure. The inner side of the first gate structure faces, at least in part, the second gate structure. A stress-inducing material fills a fin cut trench that is adjacent to the outer side of the first gate structure. An epitaxial semiconductor layer fills, at least in part, an area between the first gate structure and the second gate structure.
1. A method of forming a multi-gate finFET structure comprising:
depositing a stress-inducing material into a fin cut trench that is adjacent to an outer side of a first gate structure such that a channel, which is controlled by the first gate structure, has a first amount of strain, wherein the stress-inducing material fills a majority of the fin cut trench, wherein the stress-inducing material includes one or more of: a stress nitride layer, a tensile silicon nitride layer and a compressive silicon nitride layer, and wherein the channel includes one or more of: silicon, an alloy of silicon-germanium, a III-V compound semiconductor, and a II-VI compound semiconductor;
growing an epitaxial semiconductor layer between the first gate structure and a second gate structure, wherein the first amount of strain is increased to a second amount of strain as a result of the growth of the epitaxial semiconductor layer, wherein the epitaxial semiconductor layer is a silicon-germanium layer, wherein each of the first and second gate structures are one of: a sacrificial gate or a true gate, and wherein the first and second gate structures include silicon, doped polysilicon with metal silicide, tungsten, titanium, tantalum, aluminum, nickel, ruthenium, palladium, platinum, tungsten nitride, aluminum nitride, titanium nitride, tungsten silicide, nickel silicide, and titanium silicide;
forming the first gate structure, wherein the first gate structure includes an inner side and the outer side;
forming a second gate structure that is adjacent to the first gate structure such that the inner side of the first gate structure faces, at least in part, the second gate structure;
forming the fin cut trench that is adjacent to the outer side of the first gate structure;
forming the epitaxial semiconductor layer such that the epitaxial semiconductor layer fills, at least in part, an area between the first gate structure and the second gate structure.