IP Library Granted Patent US 9,728,450
Granted Patent B2
US 9,728,450 · App. 14/749,788 · Granted Aug 8, 2017

Insulating a via in a semiconductor substrate

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Quick Facts
Patent No.
US 9,728,450
App. No.
14/749,788
Granted
Aug 8, 2017
Kind
B2
Abstract

Insulating a via in a semiconductor substrate, including: depositing, in the via, a dielectric layer; depositing, in the via, a barrier layer; allowing the barrier layer to oxidize; and depositing, in the via, a conducting layer.

Claims (14)

1. A method of insulating a via in a semiconductor substrate, the method comprising:

depositing, in the via, a dielectric layer;

depositing, in the via, a barrier layer, wherein depositing the barrier layer includes:

depositing a tantalum nitride layer over the dielectric layer; and

depositing a first tantalum layer over the tantalum nitride layer;

allowing the barrier layer to only partially oxidize such that the first tantalum layer is oxidized and the barrier layer at the interface between the barrier layer and the dielectric layer is not oxidized; and

depositing, in the via, a conducting layer.

2. The method of claim 1 wherein the dielectric layer comprises a CVD oxide film.

3. The method of claim 1 wherein the dielectric layer comprises a CVD nitride film.

4. The method of claim 1 wherein the dielectric layer comprises a PVD dielectric film.

5. The method of claim 1 wherein allowing the barrier layer to partially oxidize further comprises removing the semiconductor substrate from an inert environment.

6. The method of claim 1 wherein allowing the barrier layer to partially oxidize further comprises initiating a plasma electrolytic oxidation process.

7. The method of claim 1 wherein depositing the conducting layer further comprises depositing a copper layer.

8. The method of claim 1 , wherein allowing the barrier layer to only partially oxidize further comprises: depositing a tantalum pentoxide layer over the first tantalum layer; the method further comprising depositing a second tantalum layer over the tantalum pentoxide layer.

Assignments (5)
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 073658/0439 →
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 073658/0823 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: TESSERA, INC.
Reel/Frame 051489/0557 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2015
From: FAROOQ, MUKTA G.; OAKLEY, JENNIFER A.; PETRARCA, KEVIN S.; REARDON, NICOLE R.; SIMON, ANDREW H.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 035965/0631 →