Graphene and metal interconnects with reduced contact resistance
View Patent ↗A structure including a first metal line in a first interconnect level, the first metal line comprising one or more graphene portions, a second metal line in a second interconnect level above the first interconnect level, the second metal line comprising one or more graphene portions, and a metal via comprising a palladium liner extends vertically and electrically connects the first metal line with the second metal line, the via is at least partially embedded in the first metal line such that the palladium liner is in direct contact with at least an end portion of the one or more graphene portions of the first metal line.
1. A structure comprising:
a first metal line in a first interconnect level, the first metal line comprising one or more graphene portions;
a second metal line in a second interconnect level above the first interconnect level, the second metal line comprising one or more graphene portions;
a metal via comprising a palladium liner extending vertically and electrically connecting the first metal line with the second metal line, the metal via is at least partially embedded in the first metal line such that the palladium liner is in direct contact with at least an end portion of the one or more graphene portions of the first metal line; and
a palladium cap in direct contact with a conductive interconnect material of the metal via and an end portion of the one or more graphene portions of the second metal line.
2. The structure of claim 1 , wherein the one or more graphene portions of both the first and second metal lines comprises a graphene sheet oriented horizontally parallel with the first and second interconnect levels, respectively.
3. The structure of claim 1 ,
wherein the palladium cap extends across a top surface of the metal via and down a vertical interface between the metal via and the second metal line.
4. The structure of claim 1 , further comprising:
a first seed layer in direct contact with a side and a bottom of the first metal line; and
a second seed layer in direct contact with a side and a bottom of the second metal line,
wherein the first and second seed layers comprise ruthenium, nickel, palladium, iridium, copper, or any combination thereof.
5. The structure of claim 1 , wherein the palladium liner of the metal via is in direct contact with a seed layer extending along a side and a bottom of the first metal line, the seed layer comprises ruthenium, nickel, palladium, iridium, copper, or any combination thereof.
6. The structure of claim 1 , wherein the metal via further comprises a barrier layer comprising tantalum, tantalum nitride, titanium, titanium nitride or any combination thereof, the barrier layer is in direct contact with the palladium liner and the conductive interconnect material of the metal via.
7. A method comprising:
forming a first metal line in a first interconnect level, the first metal line comprising one or more graphene portions;
forming a second metal line in a second interconnect level above the first interconnect level, the second metal line comprising one or more graphene portions;
forming a metal via comprising a palladium liner extending vertically and electrically connecting the first metal line with the second metal line, the metal via is at least partially embedded in the first metal line such that the palladium liner is in direct contact with at least an end portion of the one or more graphene portions of the first metal line; and
replacing a portion of a non-palladium seed layer of the second metal line with a palladium cap in direct contact with a top surface of the metal via and an end portion of the one or more graphene portions of the second metal line, the non-palladium seed layer is in direct contact with and extends along a side and a bottom of the second metal line.
8. The method of claim 7 , wherein the one or more graphene portions of both the first and second metal lines comprises a graphene sheet oriented horizontally parallel with the first and second interconnect levels, respectively.
9. The method of claim 7 , further comprising:
removing a portion of a seed layer to expose the end portion of the one or more graphene portions of the second metal line, the seed layer is in direct contact with and extends along a side and a bottom of the second metal line; and
selectively depositing a palladium cap in direct contact with a conductive interconnect material of the metal via and the end portion of the one or more graphene portions of the second metal line.
10. The method of claim 7 , further comprising:
removing a portion of a seed layer to expose the end portion of the one or more graphene portions of the second metal line, the seed layer is in direct contact with and extends along a side and a bottom of the second metal line; and
selectively depositing a palladium cap in direct contact with a conductive interconnect material of the metal via and the end portion of the one or more graphene portions of the second metal line, the palladium cap extending across a top surface of the metal via and down a vertical interface between the metal via and the second metal line.
11. The method of claim 7 , wherein the palladium liner of the metal via is in direct contact with a first seed layer, the first seed layer is in direct contact with a side and a bottom of the first metal line.
12. A method comprising:
etching, in a first dielectric layer, a first trench;
filling the first trench with graphene;
etching in a second dielectric layer a via opening, the second dielectric layer is above the first dielectric layer, and at least an end portion of the graphene in the first trench is exposed along a sidewall at a bottom of the via opening;
depositing, conformally, a layer of palladium within the via opening;
filling the via opening with a conductive interconnect material;
etching, in the second dielectric layer, a second trench which intersects with, and at least partially removes a portion of, the conductive interconnect material in the via opening; and
filling the second trench with graphene.
13. The method of claim 12 , wherein the graphene of both the first and second metal lines comprises a graphene sheet oriented horizontally parallel with the first and second interconnect levels, respectively.
14. The method of claim 12 , further comprising:
replacing a portion of a non-palladium seed layer of the second trench with a palladium cap in direct contact with a top surface of the conductive interconnect material and an end portion of the graphene in the second trench, the non-palladium seed layer is in direct contact with and extends along a side and a bottom of the second trench.
15. The method of claim 12 , further comprising:
removing a portion of a seed layer to expose the end portion of the graphene of the second trench, the seed layer is in direct contact with and extends along a side and a bottom of the second trench; and
selectively depositing a palladium cap in direct contact with the conductive interconnect material and the end portion of the graphene of the second trench, the palladium cap extending across a top surface of the conductive interconnect and down a vertical interface between the conductive interconnect material and the second trench.
16. The method of claim 12 , wherein the layer of palladium within the via opening is in direct contact with a seed layer, the seed layer is in direct contact with a side and a bottom of the first metal line.
17. The method of claim 12 , wherein etching the via opening in a second dielectric layer comprises:
exposing a seed layer in direct contact with a side and a bottom of the first trench.
18. The method of claim 12 , wherein filling the first trench and the second trench with graphene comprises:
using a chemical vapor deposition process to deposit multilayer graphene sheets oriented horizontally parallel with the first and second interconnect levels, respectively.