Insulating a via in a semiconductor substrate

1. A semiconductor substrate, comprising:

one or more vias, each of the one or more via including;

a dielectric layer deposited on the via walls;

a barrier layer deposited on the dielectric layer, wherein the barrier layer includes a tantalum nitride layer and an oxidized tantalum layer deposited on the tantalum nitride layer, and wherein an interface between the barrier layer and the dielectric layer is not oxidized; and

a conducting layer deposited on the barrier layer.

2. The semiconductor substrate of claim 1 wherein the dielectric layer comprises a chemical vapor deposition (‘CVD’) oxide film.

3. The semiconductor substrate of claim 1 wherein the dielectric layer comprises a chemical vapor deposition (‘CVD’) nitride film.

4. The semiconductor substrate of claim 1 wherein the dielectric layer comprises a physical vapor deposition (‘PVD’) dielectric film.

5. The semiconductor substrate of claim 1 wherein the conducting layer is comprised of copper.

6. The semiconductor substrate of claim 1 wherein the dielectric layer is comprised of a chemical vapor deposition (‘CVD’) nitride film.

7. The semiconductor substrate of claim 1 wherein the semiconductor substrate is a silicon wafer and the via is a through-silicon via (‘TSV’).

8. A semiconductor substrate, comprising:

a dielectric layer deposited on the semiconductor substrate; and

a capacitor structure, including:

a barrier layer deposited on the dielectric layer, wherein the barrier layer includes a tantalum nitride layer and an oxidized tantalum layer deposited on the tantalum nitride layer, and wherein an interface between the barrier layer and the dielectric layer is not oxidized; and

a conducting layer deposited on the barrier layer.

9. The semiconductor substrate of claim 8 wherein the conducting layer includes a tantalum layer and a conducting metal deposited on the barrier layer.

10. The semiconductor substrate of claim 9 wherein the conducting metal is copper.