Heterogeneous source drain region and extension region
A semiconductor structure includes a source drain region of a first material and an extension region of a second material. A semiconductor device fabrication process includes forming a sacrificial dielectric portion upon a semiconductor substrate, forming a sacrificial gate stack upon the sacrificial dielectric portion, forming a gate spacer upon the sacrificial dielectric portion against the sacrificial gate, forming a source drain region of a first doped material upon the semiconductor substrate against the gate spacer, forming a replacement gate trench by removing the sacrificial gate stack, forming an extension trench by removing the sacrificial dielectric portion, and forming an extension region of a second doped material within the extension trench.
1. A semiconductor device fabrication process comprising:
forming a sacrificial portion upon a substrate;
forming a sacrificial gate stack upon the sacrificial portion;
forming a sacrificial gate spacer upon the sacrificial portion against the sacrificial gate;
forming a source drain region of a first doped material upon the substrate against the gate spacer;
removing the sacrificial gate stack forming a replacement gate trench;
forming an extension trench between the sacrificial gate spacer and the substrate by removing the sacrificial portion accessible via the replacement gate trench;
forming an extension region of a second doped material that has a higher mobility relative to the first doped material within the extension trench against the sacrificial gate spacer and against the substrate;
removing the sacrificial gate spacer; and
forming a replacement gate spacer upon the extension region.
2. The semiconductor device fabrication process of claim 1 , further comprising:
forming a gate liner upon the extension region, upon the replacement gate spacer, and upon the substrate.
3. The semiconductor device fabrication process of claim 2 , further comprising:
forming a replacement gate upon the gate liner.
4. The semiconductor device fabrication process of claim 1 , wherein the substrate is a multilayered substrate.
5. The semiconductor device fabrication process of claim 1 , wherein the substrate is a bulk substrate.
6. The semiconductor device fabrication process of claim 1 , wherein the second doped material comprises a higher dopant concentration relative to the first doped material.
7. The semiconductor device fabrication process of claim 1 , wherein the extension region electrically contacts the source drain region.
8. The semiconductor fabrication process of claim 3 , further comprising:
forming an interlayer dielectric portion upon the source drain region against the sacrificial gate spacer.
9. The semiconductor fabrication process of claim 8 , further comprising:
forming a planarization layer upon the interlayer dielectric portion, upon an upper surface of the replacement gate spacer, upon an upper surface of the gate liner, and upon the replacement gate.
10. The semiconductor fabrication process of claim 9 , further comprising:
forming a source drain contact trench within the planarization layer and within the interlayer dielectric portion to expose the source drain region; and
forming a source drain contact by filling the source drain contact trench with electrically conductive material.
11. The semiconductor fabrication process of claim 1 , wherein the sacrificial gate comprises sacrificial gate material formed upon the sacrificial portion and a sacrificial gate cap formed upon the sacrificial gate material.
12. The semiconductor fabrication process of claim 9 , further comprising:
forming a channel contact trench within the planarization layer to expose the replacement gate; and
forming a channel contact by filling the channel contact trench with electrically conductive material.