Heterogeneous source drain region and extension region
A semiconductor structure includes a source drain region of a first material and an extension region of a second material. A semiconductor device fabrication process includes forming a sacrificial dielectric portion upon a semiconductor substrate, forming a sacrificial gate stack upon the sacrificial dielectric portion, forming a gate spacer upon the sacrificial dielectric portion against the sacrificial gate, forming a source drain region of a first doped material upon the semiconductor substrate against the gate spacer, forming a replacement gate trench by removing the sacrificial gate stack, forming an extension trench by removing the sacrificial dielectric portion, and forming an extension region of a second doped material within the extension trench.
1. A semiconductor device fabrication process comprising:
forming a sacrificial portion upon a substrate;
forming a sacrificial gate stack upon the sacrificial portion;
forming a gate spacer upon the sacrificial portion against the sacrificial gate;
forming a source drain region of a first doped material upon the substrate against the gate spacer;
removing the sacrificial gate stack forming a replacement gate trench;
forming an extension trench between the gate spacer and the substrate by removing the sacrificial dielectric portion accessible via the replacement gate trench; and
forming an extension region of a second doped material that has a higher mobility relative to the first doped material within the extension trench against the gate spacer and against the substrate.
2. The semiconductor fabrication process of claim 1 , further comprising:
forming an interlayer dielectric portion upon the source drain region against the gate spacer.
3. The semiconductor fabrication process of claim 2 , further comprising:
forming a liner within the replacement gate trench.
4. The semiconductor fabrication process of claim 3 , further comprising:
forming a replacement gate upon the liner within the replacement gate trench.
5. The semiconductor fabrication process of claim 4 , further comprising:
forming a planarization layer upon the interlayer dielectric portion, upon an upper surface of the gate spacer, upon an upper surface of the liner, and upon the replacement gate.
6. The semiconductor fabrication process of claim 5 , further comprising:
forming a source drain contact trench within the planarization layer and within the interlayer dielectric portion to expose the source drain region; and
forming a source drain contact by filling the source drain contact trench with electrically conductive material.
7. The semiconductor fabrication process of claim 5 , further comprising:
forming a channel contact trench within the planarization layer to expose the replacement gate; and
forming a channel contact by filling the channel contact trench with electrically conductive material.
8. The semiconductor fabrication process of claim 1 , wherein the sacrificial gate stack comprises a sacrificial gate formed upon the sacrificial dielectric portion and a sacrificial gate cap formed upon the sacrificial gate.
9. The semiconductor fabrication process of claim 1 , wherein the substrate is a multilayered substrate.
10. The semiconductor fabrication process of claim 1 , wherein the substrate is a bulk substrate.
11. The semiconductor fabrication process of claim 1 , wherein the second doped material comprises a higher dopant concentration relative to the first doped material.
12. The semiconductor fabrication process of claim 1 , wherein the extension region electrically contacts the source drain region.