Asymmetric high-K dielectric for reducing gate induced drain leakage
An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
1. A gate structure comprising:
an interfacial dielectric layer on substrate, a source side and a drain side of the gate structure, the interfacial dielectric having a first thickness on the source side and a second thickness on the drain side, the first thickness being different than the second thickness forming an asymmetric gate dielectric;
a gate material formed on the interfacial dielectric layer;
sidewalls on the gate material on the source side and drain side; and
high-k dielectric layer on the sidewalls on the drain side and underlying the gate material.
2. The gate structure of claim 1 , further comprising a nitridized high-k dielectric sidewall on the sidewalls on the source side of the gate structure.
3. The gate structure of claim 2 , wherein the nitridized sidewall inhibits oxide growth on the source side of the gate structure.
4. The gate structure of claim 2 , wherein the high-k dielectric sidewall is HfO 2 .