FinFET with constrained source-drain epitaxial region

1. A semiconductor structure comprising:

a plurality of fins on a substrate;

a gate over a first portion of the plurality of fins, a second portion of the plurality of fins is exposed; and

a nitride material above and in direct contact with the gate and on opposite sides of the second portion of the plurality of fins such that a top region of the second portion of the plurality of fins remains exposed, the nitride material on opposite sides of the second portion of the plurality of fins comprises sidewall spacers,

wherein the second portion of the plurality of fins comprises:

an epitaxially grown semiconductor material, wherein lateral growth of the epitaxially grown semiconductor material is prevented by the sidewall spacers, the epitaxially grown semiconductor material comprises geometrically constrained unmerged source-drain regions,

wherein a top portion of the epitaxially grown semiconductor material extends upwardly from the sidewall spacers,

wherein epitaxial growth of the top portion of the epitaxially grown semiconductor material takes place on a {1 1 1} plane, and

wherein a width of the top portion of the epitaxially grown semiconductor material is equal to or less than a width of the geometrically constrained unmerged source-drain regions.

2. The structure of claim 1 , wherein the top portion of the epitaxially grown semiconductor material extending upwardly from the sidewall spacers comprises a triangular shape.

3. The structure of claim 1 , wherein the epitaxially grown semiconductor material comprises in-situ doped silicon.

4. The structure of claim 1 , wherein the epitaxially grown semiconductor material comprises in-situ doped silicon-germanium.

5. The structure of claim 1 , wherein the substrate comprises a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate.