FinFET with constrained source-drain epitaxial region
View Patent ↗A method includes forming a plurality of fins on a substrate, a gate is formed over a first portion of the plurality of fins with a second portion of the plurality of fins remaining exposed. Spacers are formed on opposite sidewalls of the second portion of the plurality of fins. The second portion of the plurality fins is removed to form a trench between the spacers. An epitaxial layer is formed in the trench. The spacers on opposite sides of the epitaxial layer constrain lateral growth of the epitaxial layer.
1. A method comprising:
forming a plurality of fins on a substrate;
forming a gate over a first portion of the plurality of fins, a second portion of the plurality of fins remains exposed;
depositing a nitride material above and in direct contact with the gate and the second portion of the plurality of fins;
etching the nitride material until a top surface of the second portion of the plurality of fins is exposed, a portion of the nitride material remains on opposite sides of the second portion of the plurality of fins forming sidewall spacers;
etching the second portion of the plurality fins to form a trench between the sidewall spacers;
epitaxially growing a semiconductor material within the trench to replace the second portion of the plurality of fins, wherein lateral epitaxial growth of the semiconductor material is prevented by the sidewall spacers forming geometrically constrained unmerged source-drain regions; and
continuing epitaxially growing the semiconductor material until a top portion of the semiconductor material extends upwardly from the sidewall spacers, wherein epitaxial growth of the top portion of the semiconductor material takes place on a {111} plane,
wherein a width of the top portion of the semiconductor material is equal to or less than a width of the geometrically constrained unmerged source-drain regions.
2. The method of claim 1 , wherein the semiconductor material comprises:
in situ doped silicon or silicon-germanium.
3. The method of claim 1 , wherein the substrate comprises a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate.
4. The method of claim 1 , wherein etching the second portion of the plurality of fins to form the trench between the sidewall spacers comprises:
removing an upper region of the second portion of the plurality of fins while a lower region of the second portion of the plurality of fins remains in the trench,
wherein the lower region of the second portion of the plurality of fins provides a seed for epitaxially growing the semiconductor material on SOI substrates.
5. The method of claim 1 , wherein the top portion of the semiconductor material extending upwardly from the sidewall spacers comprises a triangular shape.