Asymmetric high-k dielectric for reducing gate induced drain leakage
An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
1. A method, comprising:
performing a blocking process on a sidewall on a source side of a gate structure; and
performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure adjacent to a drain region, while inhibiting oxide growth on the sidewall on the source side of the gate structure adjacent to a source region,
wherein the blocking process is a damaging implant process, which damages the sidewall on the source side of the gate structure, and further comprising removing the damaged sidewall prior to performing the oxygen annealing process.
2. The method of claim 1 , wherein the blocking process comprises deposition of a masking material overlapping the source side of the gate structure.
3. The method of claim 2 , wherein the masking material is a nitrogen material.
4. The method of claim 1 , wherein oxygen is prevented from channeling into a substrate via a high-k material on the sidewall on the source side.
5. The method of claim 4 , wherein the high-k material on the sidewall is composed of HfO 2 .
6. The method of claim 1 , wherein the oxygen annealing process is a low temperature oxygen anneal.
7. The method of claim 6 , wherein the low temperature oxygen anneal is at 500° C. for about 30 minutes.
8. The method of claim 7 , wherein a thickness of the oxide region is controlled by adjusting the low temperature oxygen anneal.
9. The method of claim 8 , wherein the thickness of the oxide region increases from about 1.5 nm to about 1.8 nm.