Performance optimized gate structures having memory device and logic device, the memory device with silicided source/drain regions that are raised with respect to silicided source/drain regions of the logic device
View Patent ↗A performance optimized CMOS FET structure and methods of manufacture are disclosed. The method includes forming source and drain regions for a first type device and a second type device. The method further includes lowering the source and drain regions for the first type device, while protecting the source and drain regions for the second type device. The method further includes performing silicide processes to form silicide regions on the lowered source and drain regions for the first type device and the source and drain regions for the second type device.
1. A transistor gate structure, comprising:
at least one leakage sensitive device with silicided raised source and drain regions in proximity to a channel region of the at least one leakage sensitive device; and
at least one logic device with silicided source and drain regions that are in closer proximity to a channel region of the at least one logic device than the silicided raised source and drain regions of the at least one leakage sensitive device are to the channel region of the at least one leakage sensitive device,
wherein the at least one leakage sensitive device and an adjacent one of the at least one logic device share a source/drain in a cavity located between the at least one leakage sensitive device and the adjacent one of the at least one logic device.
2. The transistor gate structure of claim 1 , wherein the source and drain regions of the at least one leakage sensitive device and the at least one logic device are epitaxial growth material.
3. The transistor gate structure of claim 2 , wherein the epitaxial growth material of the at least one leakage sensitive device and the at least one logic device is semiconductor material.
4. The transistor gate structure of claim 3 , wherein the epitaxial growth material is formed in trenches on source and drain regions of the at least one leakage sensitive device and the at least one logic device.
5. The transistor gate structure of claim 4 , wherein the epitaxial growth material of the at least one logic device has a surface that has been etched back.
6. The transistor gate structure of claim 5 , wherein the epitaxial growth material of the at least one logic device is doped material.
7. The transistor gate structure of claim 6 , wherein the doped material is either N-type dopants or P-type dopants.
8. The transistor gate structure of claim 1 , further comprising respective source/drain cavities coinciding with at least a space between the at least one leakage sensitive device and the at least one logic device, wherein one of the respective source/drain cavities is in a cavity between the at least one leakage sensitive device and an adjacent one of the at least one logic device.
9. The transistor gate structure of claim 8 , wherein the silicided raised source and drain regions have a height of 10-25 nm above a surface of the substrate.
10. The transistor gate structure of claim 8 , wherein the silicided raised source and drain regions and the silicided source and drain regions are doped material.
11. The transistor gate structure of claim 8 , wherein the silicided raised source and drain regions and the silicided source and drain regions are ion implanted.
12. The transistor gate structure of claim 8 , wherein gates of the at least one leakage sensitive device and the at least one logic device have silicided regions.
13. The transistor gate structure of claim 8 , wherein the silicided raised source region or silicided raised drain of the least one leakage sensitive device and the silicided source region or silicided drain region of an adjacent one of the at least one logic device are provided in the shared source/drain in a cavity between the least one leakage sensitive device and the at least one logic device.