Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack
A method of forming a semiconductor structure includes forming a first middle-of-line (MOL) oxide layer and a second MOL oxide layer in the semiconductor structure. The first MOL oxide layer including multiple gate stacks formed on a substrate, and each gate stack of the gate stacks including a source/drain junction. A first nitride layer is formed over a silicide in the first MOL oxide layer. A second nitride layer is formed. Trenches are formed through the second nitride layer down to the source/drain junctions. A nitride cap of the plurality of gate stacks is selectively recessed. At least one self-aligned contact area (CA) element is formed within the first nitride layer. The first MOL oxide layer is selectively recessed. An air-gap oxide layer is deposited. The air gap oxide layer is reduced to the at least one self-aligned CA element and the first nitride layer.
1. A method of forming a semiconductor structure comprising:
forming a first middle-of-line (MOL) oxide layer and a second MOL oxide layer in the semiconductor structure, the first MOL oxide layer including a plurality of gate stacks formed on a substrate, and each gate stack of the plurality of gate stacks including a source/drain junction;
forming a first nitride layer over a silicide in the first MOL oxide layer;
forming a second nitride layer;
forming trenches through the second nitride layer down to the source/drain junctions;
selectively recessing a nitride cap of the plurality of gate stacks;
forming at least one self-aligned contact area (CA) element within the first nitride layer;
selectively recessing the first MOL oxide layer on a first side and a second side of the at least one self-aligned CA element such that portions of the first MOL oxide layer remain on (i) top portions of the first nitride layer, (ii) portions of the silicide and (iii) portions of the nitride cap;
depositing an air-gap oxide layer introducing one or more air-gaps in the air-gap oxide layer; and
reducing the air-gap oxide layer to the at least one self-aligned CA element and the first nitride layer, wherein a portion of the air-gap oxide layer replaces a removed portion of the first MOL oxide layer.
2. The method of claim 1 , wherein reducing the air-gap oxide layer comprises performing chemical-mechanical planarization (CMP) on the air-gap oxide layer.
3. The method of claim 2 , further comprising:
depositing metal caps to the at least one self-aligned CA element and at least one gate element, wherein the at least one gate element comprises a tungsten (W) gate element.
4. The method of claim 2 , further comprising:
masking the at least one self-aligned CA element of the semiconductor structure with a mask prior to selectively recessing the first MOL oxide layer.
5. The method of claim 4 , wherein selectively recessing the nitride cap of the plurality of gate stacks comprises removing a portion of the nitride cap from a top of each of the plurality of gate stacks.
6. The method of claim 5 , wherein selectively recessing the nitride cap of the plurality of gate stacks comprises etching the nitride cap using reactive ion etching (RIE).
7. The method of claim 5 , further comprising:
removing the mask from the at least one self-aligned CA element and then performing the depositing of the air-gap oxide layer;
wherein each gate stack of the plurality of gate stacks include work function metal disposed between an interlayer dielectric and a substrate.
8. The method of claim 1 , wherein the one or more air-gaps in combination with the selective recessing of the first MOL oxide layer and the air-gap oxide layer reduces capacitance of the first MOL oxide layer.
9. A method comprising:
forming a first middle-of-line (MOL) oxide layer and a second MOL layer in a semiconductor structure, the first MOL oxide layer including a plurality of gate stacks formed on a substrate, and each gate stack of the plurality of gate stacks including a source/drain junction;
forming a first nitride layer over a first silicide in the first MOL oxide layer;
forming a second nitride layer over a second silicide in the first MOL oxide layer;
forming trenches through the second nitride layer down to the source/drain junctions;
selectively recessing a nitride cap on each of the plurality of gate stacks;
forming a first self-aligned contact area (CA) element within the first nitride layer and a second self-aligned CA element within the second nitride layer;
masking the first and the second self-aligned CA elements with a mask; and
selectively recessing the first MOL oxide layer on a first side and a second side of each of the first and the second self-aligned CA elements such that portions of the first MOL oxide layer remain on (i) top portions of the first nitride layer, (ii) portions of the first silicide and (iii) portions of the nitride caps.
10. The method of claim 9 , further comprising:
etching the nitride cap of each gate stack of the plurality of gate stacks;
removing the mask from the first and second self-aligned CA elements; and
depositing an air-gap oxide layer introducing one or more air-gaps in the air-gap oxide layer.
11. The method of claim 10 , further comprising:
reducing the air-gap oxide layer to the first and the second self-aligned CA elements and the first and the second nitride layers.
12. The method of claim 11 , wherein:
the nitride cap of each of the gate stacks of the plurality of gate stacks is formed over a metal gate of each of the gate stacks of the plurality of gate stacks and interlayer dielectric surrounding the metal gate;
the first silicide is surrounded by the first nitride layer;
the first silicide is formed in a first trench;
the second silicide is surrounded by the second nitride layer; and
the second nitride layer is formed in a second trench.
13. The method of claim 12 , wherein:
the first trench is disposed between a first pair of adjacent gate stacks of the plurality of gate stacks; and
the second trench is disposed between a second pair of adjacent gate stacks of the plurality of gate stacks.
14. The method of claim 13 , wherein reducing the air-gap oxide layer comprises performing chemical-mechanical planarization (CMP) on the air-gap oxide layer.
15. The method of claim 14 , further comprising:
depositing metal caps to the first and second self-aligned CA elements and the plurality of gate stacks.
16. The method of claim 15 , wherein metal of the metal gates of the plurality of gate stacks comprises tungsten (W) and each gate stack of the plurality of gate stacks include work function metal disposed between the interlayer dielectric and a substrate.
17. The method of claim 11 , wherein etching the nitride cap of each gate stack of the plurality of gate stacks comprises etching using reactive ion etching (RIE).
18. The method of claim 11 , wherein the one or more air-gaps in combination with the selective recessing of the first MOL oxide layer and the air-gap oxide layer reduces capacitance of the first MOL oxide layer.