Middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack
A semiconductor structure formed based on selectively recessing a middle-of-line (MOL) oxide layer of the semiconductor structure including multiple gate stacks formed on a substrate. A cap layer of the multiple gate stacks is selectively recessed. An air-gap oxide layer introducing one or more air-gaps is deposited. Chemical-mechanical planarization (CMP) is performed on the deposited air-gap oxide layer.
1. A method of forming a semiconductor structure comprising:
forming a middle-of-line (MOL) oxide layer in the semiconductor structure, the MOL oxide layer including a plurality of gate stacks formed on a substrate, each of the gate stacks of the plurality of gate stacks including a nitride cap formed over a metal gate and interlayer dielectric surrounding the metal gate, and a silicide surrounded by a nitride is formed in trenches between adjacent gate stacks of the plurality of gate stacks;
forming a nitride layer over the silicide in the MOL oxide layer;
forming at least one self-aligned contact area (CA) element within the nitride layer;
selectively recessing the MOL oxide layer on a first side and a second side of the at least one self-aligned CA element leaving remaining portions of the MOL oxide layer on the nitride layer and the nitride;
selectively recessing the nitride cap of the plurality of gate stacks;
depositing an air-gap oxide layer introducing one or more air-gaps in the deposited air-gap oxide layer; and
performing chemical-mechanical planarization (CMP) on the deposited air-gap oxide layer reducing the air gap oxide layer to the at least one self-aligned CA element and the nitride layer.
2. The method of claim 1 , further comprising:
depositing metal caps to the at least one self-aligned CA element and at least one gate element, wherein the at least one gate element comprises a tungsten (W) gate element.
3. The method of claim 1 , further comprising:
masking the at least one self-aligned CA element of the semiconductor structure prior to selectively recessing the MOL oxide layer.
4. The method of claim 3 , wherein selectively recessing the nitride cap of the plurality of gate stacks comprises removing a portion of the nitride cap from a top of each of the plurality of gate stacks.
5. The method of claim 4 , wherein selectively recessing the nitride cap of the plurality of gate stacks comprises etching the nitride cap using reactive ion etching (RIE).
6. The method of claim 4 , further comprising:
removing the mask from the at least one self-aligned CA element and then performing the depositing of the air-gap oxide layer;
wherein each gate stack of the plurality of gate stacks include work function metal disposed between the interlayer dielectric and a substrate.
7. The method of claim 1 , wherein the one or more air-gaps in combination with the selective recessing of the MOL oxide layer and the air-gap oxide layer reduces capacitance of the MOL oxide layer.
8. A method comprising:
forming a middle-of-line (MOL) oxide layer in a semiconductor structure, the MOL oxide layer including a plurality of gate stacks formed on a substrate, each of the gate stacks of the plurality of gate stacks including a nitride cap formed over a metal gate and interlayer dielectric surrounding the metal gate, and a first silicide surrounded by a first nitride is formed in a first trench, and a second silicide surrounded by a second nitride is formed in a second trench, the first trench is disposed between a first pair of adjacent gate stacks of the plurality of gate stacks, and the second trench is disposed between a second pair of adjacent gate stacks of the plurality of gate stacks;
forming a first nitride layer over the first silicide in the MOL oxide layer;
forming a second nitride layer over the second silicide in the MOL oxide layer;
forming a first self-aligned contact area (CA) element within the first nitride layer and a second self-aligned CA element within the second nitride layer;
masking the first and the second self-aligned CA elements;
selectively recessing the MOL oxide layer on a first side and a second side of each of the first and the second self-aligned CA elements leaving remaining portions of the MOL oxide layer on the first nitride layer, the second nitride layer, the first nitride and the second nitride;
etching the nitride cap of each gate stack of the plurality of gate stacks;
removing the mask from the first and second self-aligned CA elements;
depositing an air-gap oxide layer introducing one or more air-gaps in the deposited air-gap oxide layer; and
performing chemical-mechanical planarization (CMP) on the deposited air-gap oxide layer reducing the air gap oxide layer to the first and the second self-aligned CA elements and the first and the second nitride layers.
9. The method of claim 8 , further comprising:
depositing metal caps to the first and second self-aligned CA elements and the plurality of gate stacks, wherein metal of the metal gates of the plurality of gate stacks comprises tungsten (W);
and each gate stack of the plurality of gate stacks include work function metal disposed between the interlayer dielectric and a substrate.
10. The method of claim 9 , wherein etching the nitride cap of each gate stack of the plurality of gate stacks comprises etching using reactive ion etching (RIE).
11. The method of claim 8 , wherein the one or more air-gaps in combination with the selective recessing of the MOL oxide layer and the air-gap oxide layer reduces capacitance of the MOL oxide layer.