Punch through stopper in bulk finFET device
A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure. The isolation regions are recessed to provide an exposed section of the sidewall of the fin structure. A doped semiconductor material is formed on the exposed section of the lower portion of the sidewall of the fin structure. Dopant is diffused from the doped semiconductor material to a base portion of the fin structure.
1. A method for forming a semiconductor device comprising:
forming a sacrificial spacer on an upper portion of a sidewall of a fin structure;
providing an exposed section of a lower portion of the sidewall of the fin structure, wherein the sacrificial spacer remains on the upper surface of the sidewall of the fin structure;
diffusing dopant from a doped semiconductor material to a base portion of the fin structure, said diffusing dopant from the doped semiconductor material to a base portion of the fin structure comprises thermal annealing while the sacrificial spacer remains on the upper surface of the sidewall of the fin structure, wherein the dopant that is diffused from the doped semiconductor material to the base portion of the fin structure has an opposite conductivity as a source region dopant and a drain region dopant; and
removing the sacrificial spacer.
2. The method of claim 1 , further comprising forming a gate structure.
3. The method of claim 2 , wherein the gate structure is a replacement gate structure comprised of a sacrificial material.
4. The method of claim 3 , wherein the replacement gate structure is removed after said diffusing the dopant from the doped semiconductor material to the base portion of the fin structure and a functional gate is formed in the place of the replacement gate structure.
5. The method of claim 4 , wherein the forming of the replacement gate on the fin structure comprises:
depositing at least one sacrificial material layer on the fin structure; and
patterning the at least one sacrificial material layer to remove the sacrificial material from a source region portion and a drain region portion of the fin structure so that a remaining portion of the at least one sacrificial material layer is present on the channel region portion of the fin structure.
6. The method of claim 1 , further comprising forming isolation regions.
7. The method of claim 6 , wherein forming the isolation region comprises:
depositing a dielectric material in contact with an entire sidewall of the fin structure; and
recessing the dielectric material to expose the upper portion of the sidewall.
8. The method of claim 4 , wherein the forming of the sacrificial spacer comprises:
conformally depositing a blanket layer of a dielectric material; and
anisotropically etching the blanket layer of the dielectric material to remove horizontally orientated portions of the blanket layer of the dielectric material, wherein vertically orientated portions of the blanket layer of the dielectric material remain on the upper portion of the fin structure.
9. The method of claim 8 , wherein said forming the doped semiconductor material on the exposed section of the sidewall of the fin structure comprises epitaxial deposition of a silicon including material that is in situ doped with an n-type or p-type dopant.