Selective recessing to form a fully aligned via
A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.
1. An apparatus comprising:
a plurality of metal lines formed in a first dielectric layer;
first portions of the plurality of metal lines recessed in a recess region such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; and
a non-recess region comprising second portions of the plurality of metal lines that are outside the recess region,
wherein the second portions of the plurality of metal lines are not recessed.
2. The apparatus of claim 1 , further comprising a semi-conformal cap on top of the first dielectric layer and the plurality of metal lines.
3. The apparatus of claim 2 , further comprising a second dielectric layer on the semi-conformal cap.
4. The apparatus of claim 3 , wherein the first dielectric layer and the second dielectric layer are the same material.
5. The apparatus of claim 4 , wherein the metal lines are parallel to each other in a first direction.
6. The apparatus of claim 5 , further comprising a trench along a second direction formed on the second dielectric layer.
7. The apparatus of claim 6 , further comprising an interconnect level formed on an upper surface of the second dielectric layer.
8. The apparatus of claim 7 , wherein the interconnect level is located in the non-recess region.
9. The apparatus of claim 8 , further comprising a via that extends through the second dielectric layer and is interposed between the interconnect level and the first dielectric layer.
10. The apparatus of claim 9 , wherein the via extends through the semi-conformal cap.
11. The apparatus of claim 10 , wherein the via includes a lower portion that directly contacts the first portion and an upper portion that directly contact the second interconnect level.
12. The apparatus of claim 11 , wherein the via is fully aligned to both the first direction and the second direction in the selective recess region.
13. The apparatus of claim 12 , wherein the trench self-aligns the via perpendicularly to the second direction.
14. The apparatus of claim 13 , wherein the semi-conformal cap on the first dielectric layer allows the via to self-align perpendicularly to the first direction.
15. The apparatus of claim 14 , wherein the first and second dielectric layers comprise a same dielectric material.
16. The apparatus of claim 15 , wherein the dielectric material of the first and second dielectric layers are selected from a group comprising porous silicates, carbon doped oxides, silicon dioxides, silicon nitrides, and silicon oxynitrides.
17. The apparatus of claim 13 , wherein the semi-conformal cap comprises a dielectric material.
18. The apparatus of claim 17 , wherein the dielectric material of the semi-conformal cap is selected from a group comprising silicon nitride, silicon carbonitride (SiNCH), and metal oxide.
19. The apparatus of claim 14 , wherein the cap includes lower cap portions formed on an upper surface of the first portions.
20. The apparatus of claim 19 , wherein the via is located between the first portions and the lower cap portions.