Method and structure for forming dielectric isolated FinFET with improved source/drain epitaxy
Described herein is a FinFET device in which epitaxial layers of semiconductor material are formed in source/drain regions on fin portions. The fin portions can be located within a dielectric layer that is deposited on a semiconductor substrate. Surfaces of the fin portions can be oriented in the {100} lattice plane of the crystalline material of the fin portions, providing for good epitaxial growth. Further described are methods for forming the FinFET device.
1. A field effect transistor (FinFET) device, comprising:
crystalline fin portions including tapered fin tails separate from a semiconductor substrate layer, the crystalline fin portions having surfaces oriented in a crystalline plane and being located in source/drain regions of the device; and
an epitaxial layer of semiconductor material formed on the crystalline fin portions in the source/drain regions.
2. The device of claim 1 , wherein the semiconductor substrate layer includes a material selected from the group consisting of: silicon, germanium, and silicon germanium.
3. The device of claim 1 , wherein the crystalline fin portions are formed from the semiconductor substrate layer.
4. The device of claim 1 , wherein the surfaces of the crystalline fin portions provide seed surfaces for forming the epitaxial layer.
5. The device of claim 4 , wherein the seed surfaces are oriented in a { 100 } lattice plane.
6. The device of claim 1 , wherein the epitaxial layer includes a material selected from the group consisting of: silicon, germanium and silicon germanium.
7. The device of claim 1 , wherein the crystalline fin portions include crystalline silicon, and the epitaxial layer includes silicon germanium.
8. The device of claim 1 , further comprising a gate structure including a gate conductor.
9. The device of claim 8 , wherein the gate conductor includes a material selected from the group consisting of: titanium nitride, ruthenium, titanium aluminum, aluminum nitride, and tantalum carbide.
10. The device of claim 9 , further comprising a high dielectric constant material provided around the gate conductor.
11. The device of claim 1 , further comprising trenches etched in the semiconductor substrate layer to isolate individual FinFET devices.
12. The device of claim 1 , wherein the crystalline fin portions are located within a dielectric layer.
13. The device of claim 12 , wherein the crystalline fin portions are dielectrically isolated from each other by the dielectric layer.
14. A field effect transistor (FinFET) device, comprising:
crystalline fin portions dielectrically separated from a semiconductor substrate layer and located within a dielectric layer, the crystalline fin portions having surfaces oriented in a crystalline plane and being located in source/drain regions of the device, the crystalline fin portions being dielectrically isolated from each other by the dielectric layer; and
an epitaxial layer of semiconductor material formed on the crystalline fin portions in the source/drain regions.
15. The device of claim 14 , wherein the semiconductor substrate layer includes a material selected from the group consisting of: silicon, germanium, and silicon germanium, and wherein the crystalline fin portions are formed from the semiconductor substrate layer.
16. The device of claim 14 , further comprising trenches etched in the semiconductor substrate layer to isolate individual FinFET devices.
17. A field effect transistor (FinFET) device, comprising:
crystalline fin portions dielectrically separated from a semiconductor substrate layer, the crystalline fin portions having surfaces oriented in a crystalline plane and being located in source/drain regions of the device; and
an epitaxial layer of semiconductor material formed on the crystalline fin portions in the source/drain regions, wherein the surfaces of the crystalline fin portions provide seed surfaces for forming the epitaxial layer.
18. The device of claim 17 , wherein the semiconductor substrate layer includes a material selected from the group consisting of: silicon, germanium, and silicon germanium, and wherein the crystalline fin portions are formed from the semiconductor substrate layer.
19. The device of claim 17 , wherein the seed surfaces are oriented in a { 100 } lattice plane, and wherein the crystalline fin portions include crystalline silicon and the epitaxial layer includes silicon germanium.
20. The device of claim 17 , further comprising trenches etched in the semiconductor substrate layer to isolate individual FinFET devices.