Selective ILD deposition for fully aligned via with airgap
A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.
1. A semiconductor structure for integrating a fully-aligned via (FAV) with airgaps, the semiconductor structure comprising:
an airgap region including a plurality of airgaps formed between a plurality of first trenches, the airgap region devoid of inter-layer dielectric (ILD) regions; and
a non-airgap region including the FAV contacting a trench of a plurality of second trenches and the FAV contacting one or more ILD regions,
wherein a conformal cap is formed within each of the airgaps in the airgap region.
2. The semiconductor structure of claim 1 , wherein the plurality of first and second trenches are filled with a conductive material.
3. The semiconductor structure of claim 1 , wherein the conformal cap directly contacts the conductive material of the plurality of first and second trenches.
4. The semiconductor structure of claim 3 , wherein the airgap regions are confined within the conformal cap.
5. The semiconductor structure of claim 4 , wherein a dielectric cap is deposited over the ILD regions in the non-airgap region.
6. The semiconductor structure of claim 5 , wherein the dielectric cap directly contacts the conformal cap.
7. The semiconductor structure of claim 6 , wherein the dielectric cap is deposited in the airgap region and the non-airgap region.
8. The semiconductor structure of claim 1 , wherein the airgaps of the airgap region and the FAV are formed at a same metallization level.
9. The semiconductor structure of claim 1 , wherein the FAV is filled with a conductive material.
10. A semiconductor structure for integrating a fully-aligned via (FAV) with airgaps, the semiconductor structure comprising:
an airgap region including a plurality of airgaps formed between conductive regions; and
a non-airgap region including the FAV contacting a trench of a plurality of trenches, the plurality of trenches separated from each other by a plurality of dielectric pillars;
wherein inter-layer dielectric (ILD) regions are disposed over and in direct contact with the plurality of dielectric pillars in the non-airgap region,
wherein a conformal cap is formed within each of the airgaps in the airgap region.
11. The semiconductor structure of claim 10 , wherein the airgap region is devoid of ILD regions.
12. The semiconductor structure of claim 10 , wherein the conformal cap directly contacts the conductive regions.
13. The semiconductor structure of claim 12 , wherein the airgap regions are confined within the conformal cap.
14. The semiconductor structure of claim 13 , wherein a dielectric cap is deposited over the ILD regions in the non-airgap region.
15. The semiconductor structure of claim 14 , wherein the dielectric cap directly contacts the conformal cap.
16. The semiconductor structure of claim 15 , wherein the dielectric cap is deposited in the airgap region and the non-airgap region.
17. The semiconductor structure of claim 10 , wherein the airgaps of the airgap region and the FAV are formed at a same metallization level.
18. The semiconductor structure of claim 10 , wherein the FAV is filled with a conductive material.