Low aspect ratio interconnect
A low aspect ratio interconnect is provided and includes a metallization layer, a liner and a metallic interconnect. The metallization layer includes bottommost and uppermost surfaces. The uppermost surface has a maximum post-deposition height from the bottommost surface at first metallization layer portions. The metallization layer defines a trench at second metallization layer portions. The liner includes is disposed to line the trench and includes liner sidewalls that have terminal edges that extend to the maximum post-deposition height and lie coplanar with the uppermost surface at the first metallization layer portions. The metallic interconnect is disposed on the liner to fill a trench remainder and has an uppermost interconnect surface that extends to the maximum post-deposition height and lies coplanar with the uppermost surface at the first metallization layer portions.
1. A low aspect ratio interconnect, comprising:
a metallization layer comprising bottommost and uppermost surfaces, the uppermost surface having a maximum post-deposition height from the bottommost surface at first metallization layer portions, the metallization layer defining a trench at second metallization layer portions;
a liner disposed on the trench and comprising liner sidewalls having terminal edges that extend to the maximum post-deposition height and lie coplanar with the uppermost surface at the first metallization layer portions; and
a metallic interconnect disposed on the liner to fill a trench remainder and having an uppermost interconnect surface that extends to the maximum post-deposition height and lies coplanar with the uppermost surface at the first metallization layer portions.
2. The low aspect ratio interconnect according to claim 1 , further comprising:
a lower interconnect layer; and
a cap, which is disposed on the lower interconnect layer and on which the metallization layer is disposed.
3. The low aspect ratio interconnect according to claim 2 , wherein the lower interconnect layer comprises:
a dielectric material formed to define a lower trench;
a lower trench liner lining a bottom wall and sidewalls of the lower trench; and
a lower metallic interconnect disposed on the lower trench liner to fill a remainder of the lower trench.
4. The low aspect ratio interconnect according to claim 1 , wherein the liner comprises tantalum nitride and cobalt.
5. The low aspect ratio interconnect according to claim 1 , wherein the liner comprises multiple layers of different materials.
6. The low aspect ratio interconnect according to claim 1 , wherein the metallic interconnect comprises one or more of copper, cobalt and ruthenium.
7. The low aspect ratio interconnect according to claim 1 , wherein opposite trench sidewalls, the liner sidewalls and the metallic interconnect are tapered.
8. A method of forming a low aspect ratio interconnect, the method comprising:
depositing a metallization layer comprising only ultra, low-k (ULK) dielectric material defining a trench recessed from an uppermost surface of the ULK dielectric material;
forming a liner on the uppermost surface of the ULK dielectric material and in the trench;
disposing metallic interconnect material in a remainder of the trench and on an uppermost surface of the liner;
polishing the metallic interconnect material to near-coplanarity with the uppermost surface of the liner;
stopping the polishing once the near-coplanarity with the uppermost surface of the liner is reached; and
etching the liner and the metallic interconnect material to only the uppermost surface of the ULK dielectric material.
9. The method according to claim 8 , wherein the polishing comprises chemical mechanical polishing (CMP) and the etching of the liner material and the metallic interconnect material comprises a wet etching of the liner material and the metallic interconnect material selective to the ULK material.
10. The method according to claim 8 , further comprising:
depositing metallization layer dielectric to form the metallization layer;
masking first portions of the metallization layer;
forming a trench at second portions of the metallization layer;
lining uppermost surfaces of the metallization layer with the liner material to form the liner at the first and second portions; and
seeding and electroplating the metallic interconnect material over the liner.
11. The method according to claim 10 , wherein:
the forming of the trench comprises a reactive ion etch (ME),
the lining comprises liner deposition, and
the seeding and electroplating comprises physical vapor deposition (PVD).
12. The method according to claim 10 , wherein the trench, liner sidewalls and the metallic interconnect are tapered.
13. The method according to claim 8 , further comprising:
forming a lower interconnect layer with a lower trench, a lower trench liner and a lower metallic interconnect;
depositing a cap on the lower interconnect layer; and
disposing the metallization layer on the cap.
14. The method according to claim 8 , wherein the liner material comprises tantalum nitride and cobalt.
15. The method according to claim 8 , further comprising forming the liner with multiple layers of different materials.
16. The method according to claim 8 , wherein the metallic interconnect material comprises one or more of copper, cobalt and ruthenium.
17. The method according to claim 8 , wherein no further liner or metallic interconnect material is removed following the etching of the liner material to only the uppermost surface of the ULK dielectric material.
18. A method of forming a device with multiple low aspect ratio interconnects, the method comprising:
forming multiple lower interconnect layers with lower trenches, lower trench liners and lower metallic interconnects;
depositing a cap on each of the multiple lower interconnect layers;
disposing a metallization layer on an uppermost cap, the metallization layer comprising only ultra, low-k (ULK) dielectric material defining a trench recessed from an uppermost surface of the ULK dielectric material;
forming a liner on the uppermost surface of the ULK dielectric material and the trench;
disposing metallic interconnect material in a remainder of the trench and on an uppermost surface of the liner;
polishing the metallic interconnect material to near-coplanarity with the uppermost surface of the liner;
stopping the polishing once the near-coplanarity with the uppermost surface of the liner is reached; and
etching the liner and the metallic interconnect material to only the uppermost surface of the ULK dielectric material.
19. The method according to claim 18 , wherein the polishing comprises chemical mechanical polishing (CMP) and the etching of the liner material and the metallic interconnect material comprises a wet etching of the liner material and the metallic interconnect material selective to the ULK material.
20. The method according to claim 18 , wherein no further liner or metallic interconnect material is removed following the etching of the liner material to only the uppermost surface of the ULK dielectric material.