Selective recessing to form a fully aligned via
A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.
1. A method comprising:
forming a plurality of metal lines in a first dielectric layer;
recessing in a recess region a first portion of a first metal line such that a top surface of the first portion of the first metal line is below a top surface of the first dielectric layer; and
forming a tri-layer mask pattern on a low temperature oxide layer, wherein the tri-layer mask pattern includes a photoresist layer selectively patterned to form an opening such that the photoresist is on top of second portions of the plurality of metal lines and is not on top of the first portion of the plurality of metal lines, the opening having a width that overlaps every metal line among the plurality of metal lines; and
recessing in a recess region a first portion of a separate metal line such that a top surface of the first portion of the separate metal line is below a top surface of the first dielectric layer,
wherein a non-recess region comprises second portions of the first metal line that are outside the recess region.
2. The method of claim 1 , further comprising recessing in the recess region a portion of a second metal line such that a top surface of the portion of the second metal line is below the top surface of the first dielectric layer.
3. The method of claim 2 , wherein the first metal line is adjacent to a first side of the second metal line.
4. The method of claim 3 , wherein the separate metal line is adjacent to a second side of the second metal line.
5. The method of claim 4 , wherein the first side and the second side are opposite sides of the second metal line.
6. The method of claim 5 , wherein the non-recess region comprises second portions of the first metal line and the second metal line that are outside the recess region.
7. The method of claim 5 , further comprising:
forming a cap on the first dielectric layer and in the first and second recesses;
forming an etch resistant dielectric into the first and second recesses to completely fill the recesses, the etch resistant dielectric forming a barrier; and
forming a second dielectric layer on the cap and on the etch resistant dielectric.
8. The method of claim 7 , wherein the etch resistant dielectric is a nitride.
9. The method of claim 7 , wherein the metal lines are parallel to each other in a first direction, further comprising:
forming a trench along a second direction on the second dielectric layer such that the trench allows a via to self-align perpendicularly to the second direction.
10. The method of claim 9 , wherein the cap and the barrier on the first dielectric layer allows the via to self-align perpendicularly to the first direction.
11. The method of claim 10 , wherein the barrier on the first dielectric layer allows the via to at least partially overlay the barrier without causing a short between the via and the plurality of metal lines in the first dielectric layer.
12. The method of claim 7 , further comprising:
forming a cap on the first dielectric layer and in the first and second recesses; and
forming a porous SiNCH layer on the cap.
13. The method of claim 7 , wherein the metal lines are parallel to each other in a first direction.
14. The method of claim 13 , further comprising forming a trench along a second direction on the second dielectric layer such that the trench allows a via to self-align perpendicularly to the second direction.
15. The method of claim 14 , wherein the cap is on the first dielectric layer such that the via is self-aligned perpendicularly to the first direction.
16. The method of claim 15 , wherein the cap on the first dielectric layer prevents the via from passing through a void in the first and second recesses.
17. The method of claim 5 , further comprising:
forming a sacrificial nitride layer on the first dielectric layer; and
forming a low temperature oxide layer on the sacrificial nitride layer.
18. The method of claim 17 , further comprising forming a tri-layer mask pattern on the low temperature oxide layer.
19. The method of claim 18 , wherein the tri-layer mask pattern includes a photoresist layer selectively patterned such that the photoresist is on top of the plurality of metal lines except the first metal line and the separate metal line.
20. The method of claim 8 , wherein the second dielectric layer has a lower etch resistance than the etch resistant dielectric.