Semiconductor interconnect structure with double conductors
Embodiments are directed to a semiconductor structure having a dual-layer interconnect and a barrier layer. The interconnect structure combines a first conductive layer, a second conductive layer, and a barrier layer disposed between. The result is a low via resistance combined with improved electromigration performance. In one embodiment, the first conductive layer is copper, the second conductive layer is cobalt, and the barrier layer is tantalum nitride. A barrier layer is not used in other embodiments. Other embodiments are also disclosed.
1. A semiconductor interconnect comprising:
a first interconnect structure comprising:
a first trench formed in a dielectric, the first trench including a first bottom surface and opposing first sidewalls extending from the first bottom surface to an upper surface of the dielectric;
a first conductive layer comprising copper coupled to the dielectric;
a second conductive layer comprising cobalt;
a first barrier layer disposed between the first conductive layer and the second conductive layer; and
a first wetting layer comprising cobalt disposed between the dielectric and the first conductive layer,
wherein the second conductive layer comprising cobalt is directly on the first barrier layer, the first wetting layer comprising cobalt directly contacts the first conductive layer and the first barrier layer, and the second conductive layer has a width that is less than a width of the first conductive layer; and
a second interconnect structure disposed beside the first interconnect structure, the second interconnect structure comprising:
a second trench formed in the dielectric, the second trench including a second bottom surface and opposing second sidewalls extending from the second bottom surface to the upper surface of the dielectric;
a third conductive layer comprising copper coupled to the dielectric;
a fourth conductive layer comprising cobalt;
a second barrier layer disposed between the third conductive layer and the fourth conductive layer; and
a second wetting layer comprising cobalt disposed between the dielectric and the third conductive layer,
wherein the fourth conductive layer comprising cobalt is directly on the second barrier layer, the second wetting layer comprising cobalt directly contacts the third conductive layer and the second barrier layer, and the fourth conductive layer has a width that is less than a width of the third conductive layer.
2. The semiconductor interconnect of claim 1 wherein:
the first and second barrier layers are selected from a group consisting of tantalum nitride (TaN), titanium nitride (TiN), and cobalt tungsten phosphide (CoWP).
3. The semiconductor interconnect of claim 1 wherein the first and second wetting layers each have a thickness between approximately 5 angstroms and 40 angstroms.
4. A semiconductor interconnect comprising:
a first interconnect structure comprising:
a first trench formed in a dielectric, the first trench including a first bottom surface and opposing first sidewalls extending from the first bottom surface to an upper surface of the dielectric;
a first conductive layer comprising copper coupled to the dielectric;
a second conductive layer comprising cobalt; and
wherein the second conductive layer has a width that is less than a width of the first conductive layer; and
a second interconnect structure disposed beside the first interconnect structure, the second interconnect structure comprising:
a second trench formed in the dielectric, the second trench including a second bottom surface and opposing second sidewalls extending from the second bottom surface to the upper surface of the dielectric;
a third conductive layer comprising copper coupled to the dielectric; and
a fourth conductive layer comprising cobalt,
wherein the fourth conductive layer has a width that is less than a width of the third conductive layer,
wherein the second conductive layer serves as a first barrier layer in the first interconnect structure, and
wherein the fourth conductive layer serves as a second barrier layer in the second interconnect structure.
5. A semiconductor interconnect comprising:
a first interconnect structure comprising:
a first trench formed in a dielectric, the first trench including a first bottom surface and opposing first sidewalls extending from the first bottom surface to an upper surface of the dielectric;
a first conductive layer in the first trench and coupled to the dielectric;
a second conductive layer; and
a first barrier layer disposed between the first conductive layer and the second conductive layer,
wherein the second conductive layer has a width that is less than a width of the first conductive layer; and
a second interconnect structure disposed beside the first interconnect structure, the second interconnect structure comprising:
a second trench formed in the dielectric, the second trench including a second bottom surface and opposing second sidewalls extending from the second bottom surface to the upper surface of the dielectric;
a third conductive layer coupled to the dielectric;
a fourth conductive layer; and
a second barrier layer disposed between the third conductive layer and the fourth conductive layer,
wherein the fourth conductive layer has width that is less than a width of the third conductive layer.
6. The semiconductor interconnect of claim 5 , wherein:
the first conductive layer is selected from a group consisting of copper (Cu), ruthenium (Ru), tungsten (W), molybdenum (Mo), gold (Au), silver (Ag), aluminum (Al), and alloys thereof;
the second conductive layer is selected from a group consisting of cobalt (Co), ruthenium (Ru), tungsten (W), molybdenum (Mo), gold (Au), silver (Ag), aluminum (Al), and alloys thereof;
the third conductive layer is selected from a group consisting of Cu, Ru, W, Mo, Au, Ag, Al, and alloys thereof; and
the fourth conductive layer is selected from a group consisting of Co, Ru, W, Mo, Au, Ag, Al, and alloys thereof.
7. The semiconductor interconnect of claim 6 , wherein:
the first conductive layer is on the first bottom surface of the first trench;
the second conductive layer has a conductive upper surface that is substantially coplanar with the upper surface of the dielectric;
the third conductive layer is on the second bottom surface of the second trench; and
the fourth conductive layer has a conductive upper surface that is substantially coplanar with the upper surface of the dielectric.
8. The semiconductor interconnect of claim 5 , wherein the first and second barrier layers are selected from a group consisting of tantalum nitride (TaN), titanium nitride (TiN), and cobalt tungsten phosphide (CoWP).