Reduced resistance source and drain extensions in vertical field effect transistors
View Patent ↗Semiconductor devices and methods of forming the same include forming first charged spacers on sidewalls of a semiconductor fin. A gate stack on the fin is formed over the first charged spacers. Second charged spacers are formed on sidewalls of the fin above the gate stack. The fin is recessed to a height below a top level of the second charged spacers.
1. A method for forming a semiconductor device, comprising:
forming first charged spacers on sidewalls of a semiconductor fin;
forming a gate stack on the fin, over the first charged spacers;
forming second charged spacers on sidewalls of the fin above the gate stack; and
recessing the fin to a height below a top level of the second charged spacers.
2. The method of claim 1 , further comprising forming a bottom spacer after forming the first charged spacers.
3. The method of claim 2 , further comprising etching away material from the first charged spacers that is above a top level of the bottom spacer.
4. The method of claim 1 , further comprising forming an upper spacer on the gate stack after forming the second charged spacers.
5. The method of claim 4 , further comprising etching away material from the second charged spacers that is above a top level of the upper spacer.
6. The method of claim 1 , wherein recessing the fin comprises recessing the fin to a level above a top surface of the gate stack.
7. The method of claim 1 , wherein the first and second charged layers comprise a material selected from the group consisting of charged silicon nitride and charged aluminum oxide.
8. A semiconductor device, comprising: one or more semiconductor fins formed on a semiconductor substrate; a lower spacer formed above the substrate; first charged spacers formed on sidewalls of the one or more semiconductor fins; a gate stack formed above the first charged spacers and the lower spacer; and second charged spacers formed on sidewalls of the one or more semiconductor fins above the gate stack.
9. The semiconductor device of claim 8 , wherein the first charged spacers have a height that is the same as a height of the lower spacer.
10. The semiconductor device of claim 8 , further comprising an upper spacer formed over the gate stack.
11. The semiconductor device of claim 10 , wherein the second charged spacers have a height that is the same as a height of the upper spacer.
12. The semiconductor device of claim 8 , wherein the first and second charged layers comprise a material selected from the group consisting of charged silicon nitride and charged aluminum oxide.