Selective ILD deposition for fully aligned via with airgap
A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.
1. A semiconductor structure for integrating a fully-aligned via with airgaps, the semiconductor structure comprising:
a plurality of airgaps formed between a plurality of first conductive regions, each of the plurality of airgaps defined on the bottom and sides by a conformal cap;
a plurality of second conductive regions at the same level of metallization as the first conductive regions; and
a fully-aligned via, wherein the bottom of the fully-aligned via contacts the top of one of the plurality of second conductive regions.
2. The semiconductor structure of claim 1 , wherein the conformal cap is disposed on the plurality of first conductive regions.
3. The semiconductor structure of claim 1 , wherein the conformal cap is disposed on a portion of the plurality of second conductive regions.
4. The semiconductor structure of claim 1 , further comprising a plurality of selective inter-layer dielectric regions disposed on a plurality of first dielectric regions between the plurality of second conductive regions.
5. The semiconductor structure of claim 4 , wherein said semiconductor structure is devoid of selective inter-layer dielectric (ILD) regions directly above the airgaps.
6. The semiconductor structure of claim 4 , wherein the conformal cap is disposed on a portion of the selective inter-layer dielectric regions.
7. The semiconductor structure of claim 6 , further comprising a second dielectric region disposed on and surrounding the conformal cap and selective inter-layer dielectric regions.
8. The semiconductor structure of claim 7 , wherein the fully-aligned via further contacts a portion of the conformal cap, a portion of the selective inter-level dielectric regions, and a portion of the second dielectric region.
9. The semiconductor structure of claim 7 , wherein the second dielectric region defines a top surface of each of the plurality of airgaps.
10. A semiconductor structure for integrating a fully-aligned via with airgaps, the semiconductor structure comprising:
a plurality of airgaps formed between a plurality of first conductive regions, each of the plurality of airgaps defined on the bottom and sides by a conformal cap; and
a plurality of second conductive regions at the same level of metallization as the first conductive regions;
a plurality of first dielectric regions between the plurality of second conductive regions;
a plurality of selective inter-layer dielectric regions disposed on the plurality of first dielectric regions; and
a fully-aligned via, wherein the bottom of the fully-aligned via contacts the top of one of the plurality of second conductive regions.
11. The semiconductor structure of claim 10 , wherein the conformal cap is disposed on the plurality of first conductive regions.
12. The semiconductor structure of claim 10 , wherein the conformal cap is disposed on a portion of the plurality of second conductive regions.
13. The semiconductor structure of claim 10 , wherein said semiconductor structure is devoid of selective inter-layer dielectric regions directly above the airgaps.
14. The semiconductor structure of claim 10 , wherein the conformal cap is disposed on a portion of the selective inter-layer dielectric regions.
15. The semiconductor structure of claim 10 , further comprising a second dielectric region disposed on and surrounding the conformal cap and selective inter-layer dielectric regions.
16. The semiconductor structure of claim 15 , wherein the fully-aligned via further contacts a portion of the conformal cap, a portion of the selective inter-level dielectric regions, and a portion of the second dielectric region.
17. The semiconductor structure of claim 15 , wherein the second dielectric region defines a top surface of each of the plurality of airgaps.