Minimizing shorting between FinFET epitaxial regions
The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.
1. A structure comprising:
a first semiconductor fin adjacent to and parallel with a second semiconductor fin;
a first gate structure perpendicular to and covering a middle portion of the first semiconductor fin;
a second gate structure perpendicular to and covering a middle portion of the second semiconductor fin, wherein a width of the first gate structure is equal to a width of the second gate structure;
a dielectric region in direct contact with and separating the first gate structure from the second gate structure; and
a continuous spacer surrounding the first gate structure, the second gate structure, and the dielectric region, the continuous spacer is in direct contact with vertical sidewalls of each of the first gate structure, the second gate structure, and the dielectric region.
2. The structure of claim 1 , wherein the dielectric region comprises an oxide, a nitride, or an oxynitride.
3. The structure of claim 1 , wherein both the first gate structure and the second gate structure comprise copper, tungsten, gold, aluminum, ruthenium, titanium, platinum, or alloys thereof.
4. The structure of claim 1 , wherein the first gate structure and the second gate structure both comprises polycrystalline silicon.
5. The structure of claim 1 , wherein the width of both the first gate structure and the second gate structure is less than a width of the dielectric region.
6. The structure of claim 1 , further comprising:
a first epitaxial region on exposed portion of the first semiconductor fin; and
a second epitaxial region on exposed portion of the second semiconductor fin, wherein the dielectric region isolates the first epitaxial region from the second epitaxial region.
7. A structure comprising:
a first set of fins adjacent to a second set of fins
a first metal gate perpendicular to and covering a middle portion of the first set of fins;
a second metal gate perpendicular to and covering a middle portion of the second set of fins, wherein a width of the first metal gate is equal to a width of the second metal gate;
a dielectric region separating the first metal gate from the second metal gate, and wherein a top surface of the dielectric region is substantially flush with a top surface of each of the first set of fins and the second set of fins;
a first source drain region above and in direct contact with an exposed portion of the first set of fins;
a second source drain region above and in direct contact with an exposed portion of the second set of fins, wherein the dielectric region isolates the first source drain region from the second source drain region; and
a continuous spacer surrounding the first metal gate, the second metal gate, and the dielectric region, the continuous spacer is in direct contact with vertical sidewalls of each of the first metal gate, the second metal gate, and the dielectric region.
8. The structure of claim 7 , wherein the dielectric region comprises an oxide, a nitride, or an oxynitride.
9. The structure of claim 7 , wherein both the first metal gate and the second metal gate comprise copper, tungsten, gold, aluminum, ruthenium, titanium, platinum, or alloys thereof.
10. The structure of claim 7 , wherein the first metal gate and the second metal gate both comprise polycrystalline silicon.
11. The structure of claim 7 , wherein a width of both the first metal gate and the second metal gate is less than a width of the dielectric region.
12. A structure comprising:
a first fin group on a semiconductor substrate;
a second fin group on the semiconductor substrate, the first fin group is separated from the second fin group by an intermediate region;
a gate structure on a middle portion of the first fin group and a middle portion of the second fin group, the gate structure comprising a first metal gate and a second metal gate;
a dielectric region in the intermediate region in direct contact with both the first metal gate and the second metal gate;
one or more first epitaxial regions on the first fin group, the one or more first epitaxial regions are separated from each other by the first metal gate;
one or more second epitaxial regions on the second fin group, the one or more second epitaxial regions separated from each other by the second metal gate, wherein the one or more first epitaxial regions are separated from the one or more second epitaxial regions by the dielectric region; and
a continuous spacer surrounding the gate structure, and the dielectric region, the continuous spacer is in direct contact with vertical sidewalls of each of the gate structure and the dielectric region.
13. The structure of claim 12 , wherein the dielectric region comprises an oxide, a nitride, or an oxynitride.
14. The structure of claim 12 , wherein both the first metal gate and the second metal gate comprise copper, tungsten, gold, aluminum, ruthenium, titanium, platinum, or alloys thereof.
15. The structure of claim 12 , wherein the first metal gate and the second metal gate both comprise polycrystalline silicon.
16. The structure of claim 12 , wherein a width of both the first metal gate and the second metal gate is less than a width of the dielectric region.
17. The structure of claim 12 , wherein the dielectric region is above and in direct contact with the semiconductor substrate.