Advanced copper interconnects with hybrid microstructure
A device relates to a semiconductor device. The semiconductor device includes a narrow-line bamboo microstructure integrated within a metal layer of the semiconductor device and a narrow-line polycrystalline microstructure. The narrow-line polycrystalline microstructure is integrated within the same metal layer as the narrow-line bamboo microstructure.
1. A semiconductor device, comprising: a narrow-line bamboo microstructure integrated within a metal layer of the semiconductor device; and a narrow-line polycrystalline microstructure; wherein the narrow-line polycrystalline microstructure is integrated within the same metal layer as the narrow-line bamboo micro structure; wherein the narrow-line bamboo microstructure comprises nanowires configured to provide a high reliability resistance circuit; wherein the narrow-line bamboo microstructure is dispersed in greater than 1 layer of the semiconductor device and/or wherein the narrow-line polycrystalline microstructure is dispersed in greater than 1 layer of the semiconductor device, wherein a difference in aspect ratio between the narrow-line bamboo micro structure and the narrow-line polycrystalline microstructure is greater than 0.5.
2. The semiconductor device of claim 1 , wherein the narrow-line bamboo microstructure and the narrow-line polycrystalline microstructure comprise copper interconnects.
3. The semiconductor device of claim 1 , wherein the narrow-line bamboo microstructure has high electromagnetic resistance as compared to the polycrystalline structure.
4. The semiconductor device of claim 1 , wherein the narrow-line polycrystalline microstructure comprises nanowires configured to provide a high performance circuit.
5. The semiconductor device of claim 4 , wherein the narrow-line polycrystalline microstructure has higher conductivity as compared to the narrow-line bamboo microstructure.
6. The semiconductor device of claim 1 , wherein the narrow-line polycrystalline microstructure has a higher depth in the metal layer as compared to the narrow-line bamboo microstructure.
7. The semiconductor device of claim 1 , further comprising a dielectric layer comprising a liner material plated with copper.
8. The semiconductor device of claim 1 , wherein the liner material comprises tantalum, titanium, tungsten, cobalt, ruthenium, and their nitrides thereof, or a combination comprising at least one of the foregoing.
9. The semiconductor device of claim 1 , wherein the dielectric layer comprises a low-κ dielectric material.
10. The semiconductor device of claim 1 , wherein the dielectric layer comprises silicon dioxide, silsesquixoane, organosilicates, thermosetting polyarylene ethers, or a combination comprising at least one of the foregoing.
11. The semiconductor device of claim 10 , wherein the dielectric layer comprises silicon dioxide.