Advanced copper interconnects with hybrid microstructure
View Patent ↗A device relates to a semiconductor device. The semiconductor device includes a narrow-line bamboo microstructure integrated within a metal layer of the semiconductor device and a narrow-line polycrystalline microstructure. The narrow-line polycrystalline microstructure is integrated within the same metal layer as the narrow-line bamboo microstructure.
1. A method of forming a semiconductor device, comprising:
applying a masking material to a first portion of a dielectric layer;
forming a first masked portion of the dielectric layer;
forming a first narrow-line trench in a second portion of the dielectric layer, wherein the first narrow-line trench has a depth, d 1 ;
forming a second narrow-line trench in the first portion of the dielectric layer, wherein the second narrow-line trench has a depth, d 2 , wherein the depth d 1 is smaller than the depth d 2 ;
depositing a liner material into the first narrow-line trench and the second narrow-line trench and onto the dielectric layer;
plating copper onto the liner material; and
annealing the dielectric layer to form the semiconductor device, wherein a narrow-line bamboo microstructure is formed in the second portion of the dielectric layer and wherein a narrow-line polycrystalline microstructure is formed in the first portion of the dielectric layer.
2. The method of claim 1 , wherein the liner material comprises tantalum, titanium, tungsten, cobalt, ruthenium, and their nitrides thereof, or a combination comprising at least one of the foregoing.
3. The method of claim 1 , further comprising applying a masking material to the second portion of the dielectric layer before forming the second narrow-line trench.
4. The method of claim 1 , wherein the annealing is done at a temperature of 100 to 400° C. for 0.5 to 4 hours.
5. The method of claim 1 , further comprising polishing the semiconductor device with chemical mechanical planarization.
6. The method of claim 1 , wherein the dielectric layer comprises a low-κ dielectric material.
7. The method of claim 6 , wherein the dielectric layer comprises silicon dioxide.
8. The method of claim 1 , wherein the narrow-line bamboo microstructure comprises nanowires configured to provide a high reliability resistance circuit.
9. The method of claim 8 , wherein the narrow-line bamboo microstructure has high electromagnetic resistance as compared to the polycrystalline structure.
10. The method of claim 1 , wherein the narrow-line polycrystalline microstructure has higher conductivity as compared to the narrow-line bamboo microstructure.
11. The method of claim 1 , wherein the narrow-line bamboo microstructure and the narrow-line polycrystalline microstructure comprise copper interconnects.
12. The method of claim 1 , wherein the narrow-line polycrystalline microstructure comprises nanowires configured to provide a high performance circuit.
13. The method of claim 1 , wherein the narrow-line polycrystalline microstructure has a higher depth in the metal layer as compared to the narrow-line bamboo microstructure.
14. The method of claim 1 , wherein a difference in aspect ratio between the narrow-line bamboo microstructure and the narrow-line polycrystalline microstructure is greater than 0.5.
15. The method of claim 1 , wherein the narrow-line bamboo microstructure is dispersed in greater than or equal to 1 layer of the semiconductor device and/or wherein the narrow-line polycrystalline microstructure is dispersed in greater than or equal to 1 layer of the semiconductor device.
16. The method of claim 1 , wherein the narrow-line polycrystalline microstructure is integrated within the same metal layer as the narrow-line bamboo microstructure.