FinFET devices
View Patent ↗FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures.
1. A method comprising:
forming a first set of trenches in a semiconductor material and filling the first set of trenches with a first insulator material;
forming a second set of trenches in the semiconductor material and filling the second set of trenches with a second insulator material being a different material than first insulator material; and
recessing the first insulator material within the first set of trenches and the second insulator material within the second set of trenches to form fin structures.
2. The method of claim 1 , wherein the first insulator material in the first set of trenches is a first oxide material and the second insulator material in the second set of trenches is a second oxide material.
3. The method of claim 2 , wherein the first oxide material is a flowable oxide which is annealed.
4. The method of claim 1 , wherein the fin structures are partially supported by the first insulator material and the second insulator material at a bottom portion thereof.
5. The method of claim 1 , wherein the second set of trenches are formed alternating with the first set of trenches.
6. The method of claim 5 , wherein the second set of trenches formed in the semiconductor material form gate structures which are anchored by the filled trenches of the first set of trenches.
7. The method of claim 6 , wherein the second set of trenches formed in the semiconductor material to form the gate structures are anchored by the first insulator material in the filled trenches of the first set of trenches.
8. The method of claim 1 , wherein the first set of trenches are lined with a first liner material, prior to the filling with the first insulator material.
9. The method of claim 8 , wherein the second set of trenches are lined with a second liner material, prior to the filling with the second insulator material.
10. The method of claim 9 , wherein the first liner material is a different material than the second liner material.
11. The method of claim 9 , wherein the first liner material comprises a high-k dielectric material and the second liner material comprises a low-k dielectric material.
12. The method of claim 1 , wherein the first insulator material and the second insulator material are in trenches of substantially equal depth on opposite sides of respective ones of the plurality of fin structures.
13. The method of claim 12 , wherein the first insulator material and the second insulator material are different types of oxide material.
14. The method of claim 12 , wherein the first insulator material is annealed flowable oxide and the second insulator material is high-density-plasma oxide.
15. The method of claim 1 , wherein the first insulator material is annealed flowable oxide and the second insulator material is high-density-plasma oxide.
16. The method of claim 1 , wherein the filling the second set of trenches with the second insulator material comprises:
filling the second trenches with a flowable oxide followed by an anneal process; and
etching back the flowable oxide and replacing it with high-density-plasma oxide.