IP Library Granted Patent US 11,056,429
Granted Patent B2
US 11,056,429 · App. 16/817,491 · Granted Jul 6, 2021

Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device

Inventors: Benjamin David Briggs (Waterford, NY); Lawrence A. Clevenger (Saratoga Springs, NY); Bartlet H. Deprospo (Goshen, NY); Huai Huang (Saratoga, NY); Christopher J. Penny (Saratoga Springs, NY); Michael Rizzolo (Delmar, NY)
Assignee: Tessera, Inc.
H01L23/5226H01L21/7682H01L21/7684H01L21/76802H01L21/76819H01L21/76829H01L21/76834H01L21/76843H01L21/76877H01L23/5329H01L23/53219H01L23/53223H01L23/53233H01L23/53238H01L21/76825H01L21/76828H01L21/76832H01L21/76883H01L23/53252H01L2221/1047
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Quick Facts
Patent No.
US 11,056,429
App. No.
16/817,491
Granted
Jul 6, 2021
Kind
B2
Abstract

A semiconductor device includes a porous dielectric layer including a recessed portion, a conductive layer formed in the recessed portion, and a cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the cap layer.

Claims (43)

1. A method of forming a semiconductor device, the method comprising:

forming a pore-filled porous dielectric layer including a recessed portion;

forming a conductive layer in the recessed portion;

forming a cap layer on the pore-filled porous dielectric layer and on the conductive layer; and

removing at least a portion of the cap layer to expose an upper surface of the pore-filled porous dielectric layer through a gap in the cap layer to provide an exposed upper surface of the pore-filled porous dielectric layer.

2. The method of claim 1 , further comprising:

performing a treatment to remove one or more pore fillers of the pore-filled porous dielectric layer through the exposed upper surface of the pore-filled porous dielectric layer.

3. The method of claim 2 , wherein:

the treatment comprises a heat treatment;

a temperature of the heat treatment is in a range of 200 degrees Celsius to 450 degrees Celsius; and

a duration of the heat treatment is in a range of 1 minute to 30 minutes.

4. The method of claim 2 , wherein the treatment comprises a UV treatment.

5. The method of claim 1 , wherein forming the conductive layer comprises:

depositing a metal on the pore-filled porous dielectric layer;

polishing the metal; and

etching a top portion of the metal in the recessed portion.

6. A method of forming a semiconductor device, the method comprising:

forming a conductive layer in a first recessed portion of a pore-filled porous dielectric layer;

removing a top portion of the conductive layer to form a second recessed portion;

depositing a cap layer on the pore-filled porous dielectric layer and an upper surface of the conductive layer;

depositing an interlayer dielectric on the cap layer; and

polishing the interlayer dielectric and the cap layer to form a gap in the cap layer such that an upper surface of the pore-filled porous dielectric layer is exposed through the gap to provide an exposed upper surface of the pore-filled porous dielectric layer.

7. The method of claim 6 , further comprising:

performing a treatment to remove one or more pore fillers of the pore-filled porous dielectric layer through the exposed upper surface of the pore-filled porous dielectric layer.

8. The method of claim 7 , wherein:

the treatment comprises a heat treatment;

a temperature of the heat treatment is in a range of 200 degrees Celsius to 450 degrees Celsius; and

a duration of the heat treatment is in a range of 1 minute to 30 minutes.

9. The method of claim 7 , wherein the treatment comprises a UV treatment.

10. The method of claim 6 , wherein an upper surface of the interlayer dielectric is co-planar with an upper surface of the cap layer and the upper surface of the pore-filled porous dielectric layer.

11. The method of claim 6 , wherein removing the top portion of the conductive layer comprises etching the conductive layer.

12. The method of claim 6 , wherein removing the top portion of the conductive layer comprises etching the conductive layer, and a portion of the pore-filled porous dielectric layer along sidewalls of the first recessed portion.

13. The method of claim 12 , wherein the second recessed portion is wider than the first recessed portion.

14. The method of claim 1 , wherein:

an upper surface of the cap layer includes a concave portion; and

depositing an interlayer dielectric on the cap layer comprises depositing the interlayer dielectric in the concave portion of the cap layer.

15. The method of claim 14 , wherein an upper surface of the interlayer dielectric is co-planar with the upper surface of the cap layer and the upper surface of the pore-filled porous dielectric layer.

16. The method of claim 1 , wherein an upper portion of the cap layer has a width which is greater than a width of a lower portion of the cap layer.

17. The method of claim 6 , wherein:

an upper surface of the cap layer includes a concave portion; and

depositing an interlayer dielectric on the cap layer comprises depositing the interlayer dielectric in the concave portion of the cap layer.

18. The method of claim 17 , wherein an upper surface of the interlayer dielectric is co-planar with the upper surface of the cap layer and an upper surface of the pore-filled porous dielectric layer.

19. The method of claim 6 , wherein an upper portion of the cap layer has a width which is greater than a width of a lower portion of the cap layer.

Assignments (5)
CHANGE OF NAME Recorded Sep 27, 2024
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 069067/0448 →
CERTIFICATE OF CONVERSION & CHANGE OF NAME Recorded Sep 7, 2022
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 061388/0199 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 20, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: TESSERA, INC.
Reel/Frame 052176/0752 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 12, 2020
From: BRIGGS, BENJAMIN DAVID; CLEVENGER, LAWRENCE A.; DEPROSPO, BARTLET H.; HUANG, HUAI; PENNY, CHRISTOPHER J.; RIZZOLO, MICHAEL
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 052161/0782 →
Continuity (5)
Continuation 16421587 · May 24, 2019
Division 16049442 · Jul 30, 2018
Continuation 15908377 · Feb 28, 2018
Division 15199321 · Jun 30, 2016
Related Publication 20200388568A1 · Dec 10, 2020
Cited By (1)
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