Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device

1. A method of forming a semiconductor device, comprising:

forming a conductive layer in a recessed portion of a porous dielectric layer;

partially removing a top portion of the conductive layer while maintaining a height of the porous dielectric layer;

forming a conformal cap layer on the porous dielectric layer and the conductive layer in the recessed portion;

polishing the conformal cap layer to form a gap in the conformal cap layer, such that an upper surface of the porous dielectric layer is exposed through the gap and an upper surface of the conductive layer is protected by the cap layer; and

performing a heat treatment to burn out a pore filler of the porous dielectric layer through the exposed upper surface of the porous dielectric layer.

2. The method of claim 1 , wherein an upper surface of the conformal cap layer includes a concave portion.

3. The method of claim 2 , further comprising:

forming an interlayer dielectric in the concave portion of the conformal cap layer.

4. The method of claim 3 , wherein an upper surface of the interlayer dielectric is co-planar with an upper surface of the conformal cap layer and an upper surface of the porous dielectric layer.

5. The method of claim 1 , wherein an upper portion of the conformal cap layer has a width which is greater than a width of a lower portion of the conformal cap layer.

6. The method of claim 1 , wherein a temperature of the heat treatment is in a range from 200° C. to 450° C., and duration of the heat treatment is in a range from 1 minute to 30 minutes.

7. The method of claim 1 , wherein the forming of the conductive layer comprises:

depositing a metal on the porous dielectric layer and in the recessed portion;

polishing the metal and the porous dielectric layer; and

etching the porous dielectric layer and the metal in the recessed portion to form the conductive layer.

8. The method of claim 7 , wherein the forming of the conformal cap layer comprises forming the conformal cap layer on the etched porous dielectric layer and the etched metal.

9. The method of claim 1 , further comprising:

forming the porous dielectric material on an interconnect layer.

10. The method of claim 1 , wherein the gap in the conformal cap layer comprises a length which is greater than an average pore diameter of pores the porous dielectric layer.

11. The method of claim 1 , wherein an average pore diameter of pores the porous dielectric layer is greater than 1.5 nm, and a porosity of the porous dielectric layer is in a range from 0.1 vol. % and about 50 vol. %.

12. A method of forming a semiconductor device, comprising:

forming a porous dielectric layer on an interconnect layer;

forming a recessed portion in the porous dielectric layer;

depositing a metal on the porous dielectric layer and in the recessed portion;

polishing the metal and the porous dielectric layer;

etching the metal in the recessed portion and the porous dielectric layer to form a metal layer in the recessed portion;

forming a conformal cap layer on the etched porous dielectric layer and the etched metal in the recessed portion;

polishing the conformal cap layer to form a gap in the conformal cap layer, such that an upper surface of the porous dielectric layer is exposed through the gap, the gap comprising a length which is greater than an average pore diameter of the pores the porous dielectric layer; and

performing a heat treatment to burn out a pore filler of the porous dielectric layer through the exposed upper surface of the porous dielectric layer, a temperature of the heat treatment being in a range from 200° C. to 450° C., and duration of the heat treatment being in a range from 1 minute to 30 minutes.

13. The method of claim 12 , wherein an upper surface of the conformal cap layer includes a concave portion.

14. The method of claim 13 , further comprising:

forming an interlayer dielectric in the concave portion of the conformal cap layer.

15. The method of claim 14 , wherein an upper surface of the interlayer dielectric is co-planar with an upper surface of the conformal cap layer and an upper surface of the porous dielectric layer.

16. The method of claim 12 , wherein an upper portion of the conformal cap layer has a width which is greater than a width of a lower portion of the conformal cap layer.

17. The method of claim 12 , wherein the porous dielectric layer comprises at least one of methyl silsesquioxane, hydrogen silsesquioxane, benzocyclobutene, silica and an aromatic thermoset polymer.

18. The method of claim 12 , wherein the conformal cap layer comprises at least one of silicon carbide, silicon nitride and silicon carbonitride.

19. The method of claim 12 , further comprising:

a barrier layer formed on a wall of the recessed portion, the metal layer being formed on the barrier layer, the barrier layer comprising at least one of TaN, TiN, Ti and Ta,

wherein the porous dielectric layer comprises one of a low-k dielectric material and an ultralow-k dielectric material, and

wherein the metal comprises one of copper, a copper alloy, aluminum and an aluminum alloy.

20. A method of forming a semiconductor device, comprising:

forming a conductive layer in a recessed portion of a porous dielectric layer;

partially removing a top portion of the conductive layer while maintaining a height of the porous dielectric layer;

forming a conformal cap layer on the porous dielectric layer and the conductive layer in the recessed portion;

exposing an upper surface of the porous dielectric layer; and

performing a heat treatment to burn out a pore filler of the porous dielectric layer through the exposed upper surface of the porous dielectric layer.